High voltage low power consumption SOI LDMOS transistor having strained silicon structure

Abstract

The invention provides a high voltage low power consumption SOI LDMOS transistor having strained silicon structure, which comprises a source region (9), a body region (8), a drain region (5), a super-junction structure middle n column (3), a super-junction structure middle p column (4), a source electrode (10), a drain electrode (12), a grid electrode (11) and an embedded dielectric layer (6), wherein the super-junction structure middle p column (4) is silicon material lattice-unmatched monocrystal material, which is a material capable of leading silicon to generate strain, like Ge or SiGe, and the super-junction structure middle n column (3) is n-type transverse tensile strain silicon which is parallel to the source electrode and the drain electrode and generated on the basis of the super-junction structure middle p column (4). According to the invention, the requirement of reducing drain-source on-resistance is taken into consideration on the premise of maintaining the pressure resistance of devices. The transistor according to the invention is compatible with conventional SOI LDMOS transistor technology, has quite strong practicability and is easier for meeting the application requirement of power electronic system.

Description

technical field [0001] The invention relates to an electronic device, mainly a transistor. Specifically, it is a silicon-on-insulator (SOI) laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET). Background technique [0002] In recent years, motor control, electronic ballasts, power supply switching modules and other related technologies have promoted the rapid development of smart power integrated circuits (SPICs). In SPIC, LDMOS devices play an important role. In the design of LDMOS devices, the primary considerations are breakdown voltage (BV) and on-resistance (R on ) compromise problem. Recently, a new type of device called Super Junction has attracted widespread attention due to its great improvement in the compromise between breakdown voltage and on-resistance compared to traditional devices. The concept of the superjunction is based on the complete charge compensation of alternate and heavily doped n and p columns in the drift region whe...

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Problems solved by technology

[0003] However, the charge of the p-type substrate contained in the LDMOS transistor participates in the charge compensation in the superjunction structure. Therefore, the breakdown voltage of the device is greatly affected, so that the superjunction structure has not been widely used in lateral power devices.

Salama et al. proposed to implant superjunction LDMOS (Patent No. US 6,768,180 B2) on the SOI structure, which effectively limits the interaction between the charge in the superjunction and the charge in the substrate

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