Nand memory cell array, nand flash memory having nand memory cell array, data processing method for nand flash memory

Abstract

A NAND memory cell array which can be programmed in a hot carrier injection scheme, a NAND flash memory having the NAND memory cell array, and a data processing method for the NAND flash memory are provided. The NAND memory cell array includes one select transistor and at least two storage transistors. The NAND memory cell array can be programmed by controlling a bulk bias voltage and a voltage applied to a gate in the hot carrier injection scheme.

Description

technical field [0001] The present invention relates to a kind of flash memory, more specifically, relate to a kind of NAND memory array grid that can be programmed in low current, low voltage, and low power consumption, have the NAND gate memory array grid An NAND flash memory and a data processing method for the NAND flash memory. Background technique [0002] According to the array scheme of the memory cell arranged between the bit line and the ground line, the flash memory structure can be mainly divided into an NOR flash memory structure and an NAND gate flash memory structure. In NOR flash memory, memory cells are arranged in parallel between the bit line and the ground line. In NAND flash memory, cells are arranged in series between a bit line and a ground line. [0003] In NOR flash memory, a hot carrier injection scheme is used to program memory cells, that is, store data in the memory cells, and a Fowler-Nordheim (FN) tunneling scheme is used to erase memory cell...

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Problems solved by technology

However, since the change in the charge storage state of the transfer transistor causes a disturbance phenomenon, there is a limit to the increase of the gate voltage

For this reason, hot carrier injection schemes that require passing high currents and high voltages across multiple series-connected storage transistors are difficult to use in programming methods for traditional NAND gate structures.

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