Element layout capable of increasing layout efficiency and integration degree

Abstract

The invention provides an element layout capable of increasing layout efficiency and integration degree. In the prior art, elements are separated from one another for a certain distance in order to be insulated from one another, and as a result, the integration degree is low due to a complex design rule and the large insulating distance between the elements. Aimed at an isolated LDMOS, the element layout arranges a first isolating structure around the drain of the isolated LDMOS; aimed at a plurality of LDMOSs connected in parallel, the element layout arranges a second isolating structure around the drains of all the LDMOSs connected in parallel; and the diameters of both the first isolating structure and the second isolating structure are the distance from the center of the surrounded LDMOS drain to the center of the LDMOS source. The invention does not need to design a specific design rule for the isolating structures any more, consequently, the layout process is simplified, the layout efficiency is increased, moreover, the distance between the LDMOSs is reduced, and the integration degree of the elements is increased.

Description

technical field [0001] The invention relates to the field of semiconductor design, in particular to a device layout that can improve layout efficiency and integration. Background technique [0002] In the semiconductor design process, after the logic and circuit design is completed, the layout design can be performed. Layout design is the process of transforming a designed circuit diagram into a specific physical layout. According to logic and circuit function requirements, process level requirements and design rules, a mask layout for lithography is designed. Many design rules need to be defined during layout design, for example, the distance between the source and drain of power MOS transistors with different rated voltages (referred to as device spacing) is different or the size of the drift region of power MOS transistors with different rated voltages is different. [0003] When performing layout design, the insulation design of power MOS tubes operating at high voltage...

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Problems solved by technology

[0004] The above-mentioned insulation isolation between LDMOS and other components by separating a certain distance has the following problems: First, it is necessary to define design rules for the isolation distance. When the drain voltages of LDMOS are different, it is necessary to target Different isolation distances in voltage design increase the complexity of layout design and reduce layout efficiency; moreover, all LDMOS and LDMOS and other components are separated by a large distance to achieve insulation isolation, which will reduce the integration of devices. Spend

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