Multi-chip packaging structure and manufacturing method thereof

A technology of multi-chip packaging and manufacturing methods, applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve the problems of increasing the overall thickness of the multi-chip packaging structure, increasing the collapse of wire arcs, etc., and avoiding the collapse of welding wires , the overall thickness reduction, the effect of reducing height and length

Active Publication Date: 2010-06-16
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, in the multi-chip package structure, the farther the distance between the bonding pad on the chip and the carrier is, the longer the bonding wire electrically connected between the bonding pad and the carrier must be, thus increasing the wire sweep. risk and increase the overall thickness of the multi-chip package structure

Method used

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  • Multi-chip packaging structure and manufacturing method thereof
  • Multi-chip packaging structure and manufacturing method thereof
  • Multi-chip packaging structure and manufacturing method thereof

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Embodiment Construction

[0060] Figure 1A to Figure 1I It is a schematic cross-sectional view of a manufacturing method of a chip packaging structure according to an embodiment of the present invention, and Figure 2A and Figure 2B for Figure 1B top view. First, please refer to Figure 1A , providing a carrier 110, and disposing a first chip 120 with a first active surface 122, a plurality of first pads 124 on the first active surface 122 and a first back surface 126 on the carrier 110 on. In this embodiment, the carrier 110 is a circuit board, wherein the circuit board can be FR4, FR5, BT, PI circuit substrate, and the material of the lead frame is copper or other suitable conductive materials. From Figure 1A It can be seen that when the carrier 110 is a circuit board, it may have a plurality of third pads 112 .

[0061] Next, please refer to Figure 1B , will have an opening 132 (such as Figure 2A as shown) or a notch 132' (such as Figure 2B As shown), the relay circuit substrate 130 ...

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Abstract

The invention discloses a multi-chip packaging structure which comprises a loader, a first chip, a relay circuit base board, a plurality of first bonding wires, a plurality of second bonding wires, a second chip, a plurality of third bonding wires, and a bonding layer. The first chip is arranged on the loader. The relay circuit base board is arranged on the first chip. The first bonding wire is electrically connected between the first chip and the relay circuit base board. The second bonding wire is electrically connected between the relay circuit base board and the loader. The second chip is arranged on the loader and is stacked with the first chip. The third bonding wire is electrically connected between the second chip and the loader. The bonding layer is adhered between the first chip and the second chip. Besides, the invention provides a manufacturing method for the multi-chip packaging structure.

Description

technical field [0001] The present invention relates to a semiconductor device and its manufacturing method, and in particular to a multi-chips package and its manufacturing method. Background technique [0002] In the semiconductor industry, the production of integrated circuits (IC) can be mainly divided into three stages: design of integrated circuits, fabrication of integrated circuits, and packaging of integrated circuits. [0003] In the fabrication of integrated circuits, chips are completed through wafer fabrication, integrated circuit formation, and wafer sawing. The wafer has an active surface, which generally refers to the surface of the wafer with active elements. After the integrated circuit inside the wafer is completed, the active surface of the wafer is further equipped with a plurality of bonding pads, so that the chips formed by dicing the wafer can be electrically connected to the outside through these pads. A carrier. The carrier is, for example, a lea...

Claims

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Application Information

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IPC IPC(8): H01L25/00H01L25/18H01L25/065H01L23/488H01L21/60
CPCH01L2924/15311H01L2224/4824H01L2924/10253H01L2224/45144H01L2924/01079H01L2224/48091H01L2224/48227
Inventor 周世文
Owner CHIPMOS TECH INC
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