Chip instruction and data pushing device of embedded processor

Abstract

The invention discloses a chip instruction and data pushing device of an embedded processor, which is used for solving the technical problem of high data flow in a bus of the prior art. The invention adopts the technical scheme that a pushing address storing and generating unit and a pushing time controlling unit are additionally arranged on a two-level mixed Cache terminal; an instruction pushing Buffer is additionally arranged on a one level instruction Cache terminal; and a data pushing Buffer is additionally arranged on a one-level data Cache terminal. Because of the pushing address storing and generating unit and the pushing time controlling unit, the instruction and data scheduling initiative is transferred from a high-level memory system to a low-level memory system; and because the low-level memory system can effectively dispatch accesses, the problem of access conflict of the one-level Cache is solved, and the one-level Cache is not required to send a large amount of access requests, and the data flow on a bus is reduced. The increase of the instruction pushing Buffer and the data pushing Buffer solves the problem of Cache pollution caused by pushing.

Description

technical field [0001] The invention relates to an instruction and data pushing device, in particular to an instruction and data pushing device in an embedded processor chip. Background technique [0002] Document 1 "US Patent No. 5778423" discloses an instruction prefetching device, which prefetches new instructions by predicting branch targets, which can improve performance. However, this method will increase the number of requests from the upper-level storage system to the lower-level storage system, increase the data flow, and be affected by branch misprediction. The patent also mentions that unused bits in standard-length instructions can be used to mark addresses that may be jumped to. This method requires the modification of the format of some instructions, which requires not only hardware support but also software support. support. [0003] Document 2 "US Patent No. 7246205B2" discloses a device for pushing Cache, which can determine when to use the push Cache oper...

AI Technical Summary

Problems solved by technology

However, this device causes the high-level storage system to perform too many access operations to the low-level storage system

In a Harvard-structured storage system, this problem will lead to conflicts between too many first-level instruction and data caches accessing the second-level mixed cache at the same time, reducing the timeliness of data prefetch and increasing the traffic of data transmission on the bus

The reduction of prefetching timeliness leads to the loss of processor performance. When this loss is serious, it may offset the performance improvement brought by prefetching.

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