Alignment mark, making method and detection device thereof

Abstract

The present invention discloses a method for making alignment mark, comprising: 1) etching an alignment mark on the back side of a silicon chip; and 2) deposing a layer of oxide-film on the alignmentmark. The invention also discloses an alignment mark made by the method, which is arranged on the back side of a silicon chip. In addition, the invention further discloses a detection device for alignment mark, which comprises a light source, the light emitted by the light source passes through a half transparent and half reflecting mirror, is focused by a first convex lens, passes through a holeon a carrier corresponding to the alignment mark on the back side of a silicon chip, is focused to the alignment mark on the back side of the silicon chip, and is reflected by the alignment mark, signal light sent by the alignment mark passes through the half transparent and half reflecting mirror, and is focused by a second convex lens, and finally an imaged is formed on the plane of the detection device. An alignment mark made by the method is on the back side of a silicon chip, occupying no use area of the front side of the silicon chip, and the method for detecting an alignment mark can beused for detecting the alignment mark.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to an alignment mark, a method for making the alignment mark, and a detection device for the alignment mark. Background technique [0002] Alignment marks are often used in the field of semiconductor manufacturing. In the existing technology, the alignment marks are mainly placed in the dicing lines on the front side of the silicon wafer. Especially in the development of new processes, it is often necessary to add many alignment marks. batch to evaluate. However, in the current process, the alignment marks are placed in the dicing lanes on the front side of the silicon wafer, which reduces the area used for the front side silicon wafer. Especially when developing a new process, there will be many layers on the front side of the silicon wafer. alignment marks, and the positions of the alignment marks are different. At this time, the dicing...

AI Technical Summary

Problems solved by technology

However, in the current process, the alignment marks are placed in the dicing lanes on the front side of the silicon wafer, which reduces the area used for the front side silicon wafer. Especially when developing a new process, there will be many layers on the front side of the silicon wafer. alignment marks, and the positions of the alignment marks are different

At this time, the cutting lanes for placing the alignment marks are often not enough

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