Parallel interpolation bit synchronization system in all-digital demodulation and synchronized method thereof

Abstract

The invention provides a parallel interpolation bit synchronization system in all-digital demodulation and a synchronized method thereof. The method comprises the following steps: (1) delaying two paths of input parallel sampling data K1 and K2 respectively for three clock cycles, and obtaining K1_d1, K1_d2, K1_d3 and K2_d1, K2_d2 and K2_d3; (2) respectively carrying out interpolation processing to the above sampling data and uk; (3) delaying indicating effective signals to the time when the above interpolation processing obtains results, carrying out extraction to the interpolation processing results in the step (2) according to the indicating effective signals, obtaining maximum points of symbols and traversing points of symbols and outputting the maximum points of the symbols; (4) calculating timing errors according to the maximum points of symbols and traversing points of symbols obtained in the step (3), carrying out noise filtration on the timing errors and obtaining NCO control signals after adjusting amplitude processing; and (5) determining the interval uk of the indicating effective signals and the maximum points of symbols with the former sampling point, entering next clock cycle and starting execution from the step (1).

Description

technical field [0001] The invention relates to the field of digital communication, specifically belongs to the field of all-digital demodulators, and refers to a system and method for synchronizing parallel digital bits. Background technique [0002] All-digital demodulation refers to a demodulation method in which the entire demodulation process is handled by digital circuits. At the receiving end, the analog intermediate frequency signal is converted into a digital signal after high-speed AD sampling, and then the digital signal is sent to a digital circuit, such as FPGA, and then the FPGA completes the entire demodulation process, including digital down-conversion, matched filtering, and interpolation. Modules such as bit synchronization and carrier synchronization. Since the entire demodulation process is implemented inside the FPGA, the all-digital demodulator has the advantages of high reliability, high flexibility, small size, and generalization of the hardware plat...

AI Technical Summary

Problems solved by technology

However, in the future, the processing speed of the demodulator will be higher and higher, and the serial processing method will certainly not be able to meet the actual needs, so the parallel processing method must be used to achieve

For interpolation bit synchronization, the serial algorithm cannot be directly applied to the parallel structure, so it needs to be re-studied

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