Deinterleaver for a multi-stage interleaving scheme with processing of bit pairs

一种解交织器、比特位的技术，应用在使用交错技术纠错/检错、编码、电气元件等方向，能够解决不可按比例缩小、硅片面积的代价高等问题

Inactive Publication Date: 2009-08-26
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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This document also describes a de-interleaver, which is composed of three modules of cascaded cyclic de-shifting unit, tone de-interleaving unit and symbol de-interleaving unit. scale down

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  • Deinterleaver for a multi-stage interleaving scheme with processing of bit pairs
  • Deinterleaver for a multi-stage interleaving scheme with processing of bit pairs
  • Deinterleaver for a multi-stage interleaving scheme with processing of bit pairs

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[0035] Although the invention will be described with reference to ultra-wideband networks according to the "Multiband OFDM Physical Layer Specification" from the aforementioned Multiband OFDM Consortium, it will be appreciated that the invention is applicable to other communication networks in which multi-level interleaving is used.

[0036] In the following description of the present invention, it is assumed that data to be transmitted has been referenced using figure 1 Interleaved with the three-level interleaving scheme described in equations (1), (2) and (3), the data is interleaved over 6 symbols, or 3 symbols (the above equations are modified accordingly).

[0037] In the example network, there are 9 possible data rates that can be used: 39.4Mb / s, 53.3Mb / s, 80Mb / s, 106.7Mb / s, 160Mb / s, 200Mb / s, 320Mb / s, 400Mb / s and 480Mb / s. The data rate of 39.4Mb / s is the data rate for the packet header only. Using the parameter N in the above interleaving scheme TDS , N Tint , N c...

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Abstract

The present invention provides a deinterleaver (10) for a wireless communication device that is simple and inexpensive to implement. In particular, a deinterleaver for deinterleaving a stream of data bits representing a plurality of symbols that have been interleaved using a multi-stage interleaving scheme is provided, the deinterleaver comprising preprocessing means (12) for ordering the data bits in the stream into pairs, such that the data bits in the pair are consecutive data bits from a symbol; at least one memory (16,18) for storing the paired bits, such that each pair of data bits is stored in a respective location in the memory; and a read and write address generator (20) for the at least one memory, the generator being adapted to determine the addresses in the at least one memorythat pairs of data bits are to be stored, and to determine the addresses in the at least one memory that pairs of data bits are to be read from.

Description

technical field [0001] The present invention relates to a communication device, in particular to a deinterleaver for the communication device. Background technique [0002] Interleaving is commonly used in communication systems to protect transmissions from burst errors. Burst errors will result in several consecutive bits being received incorrectly while the remaining bits of the transmission are received successfully. [0003] The data correction bits for the data are obtained before transmission, and the receiver uses these data correction bits to detect whether the data has been successfully received and whether the erroneously received bits can be corrected. In each symbol to be transmitted, only a certain number of erroneous bits can be corrected. Thus, interleaving is used to spread the bits for each symbol in transmission. Therefore, if a burst error occurs, only a small number of bits per symbol are affected, so the receiver can use the data correction bits to co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/27
CPCH03M13/276H03M13/271H03M13/2796
Inventor 普天岩赛格尔·V·萨维茨基
Owner NXP BV
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