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Non-volatile memory and method for reduced erase/write cycling during trimming of initial programming voltage

A programming voltage, non-volatile technology, applied in the field of determining the optimal initial programming voltage of various memory cell groups, which can solve the problem of exhaustion of service life

Inactive Publication Date: 2009-08-19
WODEN TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Up to half of the useful life of a memory device can be used up before it reaches the consumer

Method used

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  • Non-volatile memory and method for reduced erase/write cycling during trimming of initial programming voltage
  • Non-volatile memory and method for reduced erase/write cycling during trimming of initial programming voltage
  • Non-volatile memory and method for reduced erase/write cycling during trimming of initial programming voltage

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Embodiment Construction

[0042] memory system

[0043] Figure 1 to Figure 7 An example memory system is illustrated in which various aspects of the invention may be implemented.

[0044] figure 1 The functional blocks of a non-volatile memory chip are schematically illustrated. The memory chip 100 includes a two-dimensional memory cell array 200, a control circuit 210, and peripheral circuits such as decoders, read / write circuits, and multiplexers. The memory array 200 can be composed of word lines (see figure 2 ) via row decoders 230A and 230B and can be addressed by bit lines (see figure 2 ) are addressed via column decoders 260A and 260B. Read / write circuits 270A and 270B allow pages of memory cells to be read or programmed in parallel. In a preferred embodiment, a page is made up of adjacent rows of memory cells sharing the same word line. In another embodiment, where a row of memory cells is divided into multiple pages, block multiplexers 250A and 250B are provided to multiplex read / wr...

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Abstract

High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase / program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.

Description

technical field [0001] The present invention relates generally to non-volatile semiconductor memory, such as electrically erasable programmable read-only memory (EEPROM) and flash EEPROM, and in particular to determining optimal initial programming voltages for various groups of memory cells. Background technique [0002] Recently, solid-state memories with charge non-volatile storage capabilities, especially in the form of EEPROMs and flash EEPROMs packaged in small form factor cards, have become an important part of a wide variety of mobile and handheld devices, especially information appliances and consumer electronics) of choice for storage devices. Unlike RAM (random access memory), which is also solid-state memory, flash memory is non-volatile and retains its stored data even after power is turned off. Despite its high cost, flash memory is increasingly used in mass storage applications. Conventional mass storage devices based on rotating magnetic media, such as hard...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/10G11C29/50
CPCG11C16/0483G11C16/04G11C5/145G11C29/028G11C29/02G11C29/021
Inventor 李彦洛克·杜查尔斯·莫阿纳·胡克
Owner WODEN TECH INC
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