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Bus arbitration method and bus arbitration apparatus

A bus arbitration and configuration unit technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve problems such as system buffer data overflow, access request locking, and access rights cannot be obtained, so as to prevent data overflow and improve system performance Effect

Inactive Publication Date: 2009-08-19
WUXI ZGMICRO ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The above three existing arbitration methods have their own advantages and disadvantages. Method (1) allows each module to obtain access rights equally, but cannot reflect the difference between each access request
Method (2) is simple and easy to implement, and method (3) is more suitable for the access bandwidth requirements of different modules, but both methods (2) and (3) may cause some low-priority access requests to be denied access all the time, resulting in low Priority access requests are locked, which may cause system buffer data overflow

Method used

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  • Bus arbitration method and bus arbitration apparatus
  • Bus arbitration method and bus arbitration apparatus
  • Bus arbitration method and bus arbitration apparatus

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] Such as figure 1 As shown, the bus arbitration device includes a parameter configuration module, a storage module, and a priority adjustment module connected in sequence, and an access authority distribution module connected to the storage module; wherein, the parameter configuration module is connected to the priority adjustment module, and the parameter configuration module includes a dynamic Priority hive and dynamically adjusted interval hive.

[0041] The dynamic priority configuration unit is configured to assign a dynamic priority to the received access request and store it in the storage module, and set the static priority of the functional module that sends the access request to the initial value of the dynamic priority of the access request .

[0042] The dynamic adjustment time interval configuration unit is configured to assign a dynamic adjustment time interval to received access requests, and the dynamic adjustment time intervals assigned to different acc...

no. 2 example

[0050] Considering that some functional modules need to access the memory through the buffer, after the access waiting time exceeds the maximum access delay time that it can tolerate, data overflow will occur in the buffer and cause a system error. On the basis of the first embodiment, the reference With this parameter of waiting time threshold, access requests exceeding the waiting time threshold are given priority to obtain access rights to prevent data overflow in the buffer.

[0051] Such as figure 2 As shown, the structure diagram of the bus arbitration device and figure 1 Compared with adding a described waiting time threshold configuration unit and group priority setting unit in the parameter configuration module; wherein the function of the dynamic priority configuration unit and the dynamic adjustment time interval configuration unit is the same as figure 1 The function in the first embodiment is the same.

[0052] The waiting time threshold configuration unit is u...

no. 3 example

[0076] Different from Embodiment 1 and Embodiment 2, Embodiment 3 only considers the adjustment of the group priority of the access request, and does not adjust the dynamic priority of each access request; When allocating access rights to each access request with a waiting time threshold, and when allocating access rights to each access request whose waiting time does not exceed the access waiting time threshold, the access rights are assigned in the order of static priority from high to low. If more than one If the static priorities of the access requests are the same, the access rights are allocated according to the order of the fixed priorities of each access request from high to low; or, the access rights are allocated in a polling manner. The access right allocation module in the bus arbitration device in this embodiment is used for assigning access requests for access rights each time, giving priority to assigning access rights for group priority for the first-level acces...

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Abstract

The invention discloses a bus arbitration method and a bus arbitration device. The bus arbitration method comprises the following steps: the bus arbitration device regulates the each access request to obtain the priority of access authority according to the waiting time of each access request; wherein the priority distributed to the access request is raised as the increase of the waiting time of the access request; and the bus arbitration device distributes the access authority according to the access request priority sequence from high level to low level. The bus arbitration device comprises a priority regulation module and an access authority distribution module. With the method of the invention, the difference of access requests can be taken into account and the situation that the access request with the low priority cannot obtain the access authority can be avoided simultaneously so as to avoid the data overflow of the system buffer and enhance the system performance.

Description

technical field [0001] The invention relates to a data processing method and device applied to a system on chip (SOC for short), in particular to a bus arbitration method and a bus arbitration device. Background technique [0002] In the integrated system on chip, there are multiple functional modules that need to access memory, such as processor, direct memory access (Direct Memory Access, DMA for short), hardware accelerator, and the like. The memory resources of the system include off-chip memory, such as Synchronous Dynamic Random Access Memory (SDRAM for short), Double Date Rate Synchronous Dynamic Random Access Memory (DDR for short), NOR flash memory, etc., and for the convenience of each functional module There may also be on-chip shared memory, such as read-only memory (Read Only Memory, ROM for short), random access memory (Random Access Memory, SRAM), etc. [0003] In the integrated system on chip, the processor and other functional modules operate independently ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/18
Inventor 林川
Owner WUXI ZGMICRO ELECTRONICS CO LTD
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