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Encoding method, encoder, and transmitter

A coding method and coding technology, applied in coding, coding components, code conversion, etc., can solve problems such as parallel processing difficulties, difficult coding calculation speed, etc., and achieve the effect of improving coding speed

Active Publication Date: 2009-07-22
PANASONIC INTELLECTUAL PROPERTY CORP OF AMERICA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0027] However, in the methods described in Non-Patent Document 1 and Non-Patent Document 2, there is a problem that it is difficult to perform parallel processing because the parity bit is obtained by solving the recurrence formula, and as a result, it is difficult to improve the efficiency of encoding. calculation speed

Method used

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  • Encoding method, encoder, and transmitter

Examples

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Embodiment approach 1

[0156] Figure 4 It is a diagram showing a configuration example of an encoding device according to Embodiment 1 of the present invention. In this embodiment, an LDPC code word is obtained by multiplying a row vector of an LDPC code generation matrix by a column vector obtained by converting an input data sequence into a column vector. The present embodiment is characterized in that by adopting the above configuration, parity bits of the LDPC code can be obtained at one time, thereby enabling high-speed encoding.

[0157] In addition, in this embodiment, before parity data is generated from the input data, the input data is first stored in the encoding device. This is because when generating an LDPC codeword, the parity data is arranged after (or before) the input data and output, so it is necessary to match the timing of generating the LDPC code.

[0158] For example, when all input data is input to an encoding device and parity data is generated, there is a generation dela...

Embodiment approach 2

[0172] Figure 5 It is a diagram showing a configuration example of an encoding device 200 according to Embodiment 2 of the present invention. In addition, in the second embodiment, the same parts as those in the first embodiment are assigned the same reference numerals (including terms), and redundant descriptions are appropriately omitted.

[0173] In this embodiment, the input data is multiplied by the column vector of the generator matrix, and the result is cumulatively added to obtain parity bits. In this embodiment, the multiplication between the generator matrix and the input data is performed using the column vectors of the generator matrix. Therefore, the input data vector is generated without holding the input data when multiplication is performed. As described above, the encoding device 200 of this embodiment is characterized in that it can reduce the circuit size because it does not require a storage unit for input data, and that it can perform high-speed encodin...

Embodiment approach 3

[0187] Figure 6 It is a diagram showing a configuration example of an encoding device 300 according to Embodiment 3 of the present invention. In addition, in the third embodiment, the same parts as those in the first embodiment are assigned the same reference numerals (including terms), and redundant descriptions are appropriately omitted.

[0188] In this embodiment, the parity check data is obtained by multiplying the input data by the generator matrix calculated from the QC (Quasi Cyclic) simulated lower triangular check matrix. Then, LDPC encoding is performed using the reference vectors of the blocks that generate the matrix. The multiplication between the generator matrix and the input data multiplies the vector obtained by cyclically shifting the reference vector of the block of the generator matrix and the input data, and performs cumulative addition on the result to obtain parity data. By adopting the above configuration, in the encoding device 300, the circuit sca...

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Abstract

An encoding method by which an encoding speed is improved is disclosed. An encoder (100) comprises an input data storage section (107) for outputting the stored input data (D100) according to an output control signal (108), an input data count section (101) for counting the inputs of input data (D100), an output control section (102) for controlling the output destination of the input data (D100)according to the input counts, one-bit storage sections (103-1 to 103-(N-K)) for holding one-bit data, row-vector storage sections (104-1 to 104-K) for holding row vectors of an LDPC code creation matrix, vector multiplying sections (105-1 to 105-K) for multiplying a row vector and a column vector, a parity storage section (109) for holding a parity created by the multiplication, and an LDPC code-word series creating section (106) for creating an LDPC code word from the input data series and parity series and outputting it.

Description

technical field [0001] The present invention relates to an encoding method, an encoding device and a sending device, in particular to an encoding method, an encoding device and a sending device for generating parity bits of input data based on a check matrix of an LDPC (LowDensity Parity Check) code as a standard . Background technique [0002] In recent years, an LDPC code defined by a parity check matrix has been used as an error correction code (Error Correction Code). The LDPC code is a linear code defined by a very coarse check matrix, that is, a check matrix with very few non-zero elements in the matrix. The prior art performs encoding directly on the basis of such a check matrix. [0003] Specifically, in existing codes such as figure 1 When the check matrix shown above generates parity bits, the determinant is transformed to reduce the number of operations (for example, Non-Patent Document 1). [0004] figure 1 The LDPC check matrix is ​​a matrix with q rows and...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/19
CPCH03M13/1185H03M13/1188
Inventor 四十九直也冈村周太村上丰
Owner PANASONIC INTELLECTUAL PROPERTY CORP OF AMERICA
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