Multi-rate compatible digital intermediate frequency implementing apparatus and method

Abstract

The invention relates to a multi-rate compatible FPGA implementation device and a method, which belong to the digital intermediate-frequency signal processing field. The multi-rate compatible FPGA implementation device consists of sub-modules and is characterized in that the sub-modules are set to the highest rate and are downward compatible to other rates; each sub-module includes an I / O control module; the I / O control module of the sub-module of the first stage is used for generating an initial data input time sequence control logic according to the bandwidth of a baseband signal configured by upper software, and outputting an output effective signal to the sub-modules of the following stages by using the data input time sequence control logic as the initial input effective signal; and the I / O control module of the sub-module of the next stage is used for reading the output effective signal of the previous stage as the input effective signal of the current stage, and outputting the output effective signal to the following stage. The invention further provides the processing method of the device. The device and the method have the advantages of simple design, convenient simulation and multi-rate compatibility.

Description

technical field [0001] The invention relates to an FPGA (Field Programed Gate Array) implementation device and method for a multi-rate compatible system, in particular to a multi-rate compatible FPGA implementation device and method in the field of digital intermediate frequency signal processing. Background technique [0002] The LTE (Long Term Evolution) system has multiple bandwidth configuration requirements such as 5Mhz, 10Mhz, and 20Mhz on the baseband. Corresponding to the intermediate frequency part of the transmission, the input of the baseband signal has multiple rates. In theory, it is possible to make a set of solutions for the processing of these various bandwidths, such as figure 1 Shown: Design according to the fixed bandwidth, design a set of code for each bandwidth, the data files after the code compilation are stored in the flash at the same time, the underlying CPU can choose to download the corresponding data files to the FPGA according to the current sys...

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Problems solved by technology

In theory, it is possible to make a set of solutions for the processing of these various bandwidths, such as figure 1 Shown: Design according to the fixed bandwidth, design a set of code for each bandwidth, the data files after the code compilation are stored in the flash at the same time, the underlying CPU can choose to download the corresponding data files to the FPGA according to the current system bandwidth , to make it work normally by changing the underlying FPGA configuration, but there will be a series of problems such as heavy workload, unfavorable for later maintenance, unstable switching, etc.

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