Circuit for buffering having a coupler

Abstract

The buffer circuit includes a differential amplifier differentially amplifying a reference node corresponding to a reference voltage and an input node corresponding to the input signal by sensing a potential difference of the reference voltage and the input signal. A coupling unit couples the input signal to the reference node, making it possible to improve the operating speed of the buffer circuit and operate normally when a level of the input signal or the reference voltage becomes low.

Description

technical field [0001] The present invention relates to a semiconductor device, and more particularly to a buffer circuit capable of buffering an input signal. Background technique [0002] Generally, a semiconductor device includes a buffer circuit that receives external signals (eg, data, addresses, commands, etc.) and converts the external signals into signals suitable for an internal logic. [0003] A conventional buffer circuit includes a differential amplifier that senses and amplifies the potential difference between a reference voltage VREF and an input signal IN, such as figure 1 shown. [0004] Specifically, two PMOS (P-type metal-oxide-semiconductor) transistors P1 and P2 are formed in a current mirror structure to supply the same current to the two nodes ND1_OLD and ND2_OLD, and are based on NMOS (N-type metal-oxide-semiconductor) The potential difference between the reference voltage VREF received by the transistor N1 and the input signal IN received by the NM...

AI Technical Summary

Problems solved by technology

In this case, the NMOS transistors N1, N2 limit the current flowing, which slows down the operation of the snubber circuit

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