Substrate for semiconductor package structure, semiconductor package structure and manufacturing method thereof

A packaging structure and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as reduced bonding reliability, partial peeling, and damage to the electrical connection between the chip 13 and external components

Inactive Publication Date: 2009-04-15
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the specification of the packaging structure becomes thinner, the thickness of the bonding layer is also gradually thinned. When the thickness of the bonding layer 12 becomes thinner, delamination is more likely to occur between the substrate 11 and the chip 13, and then local peeling occurs. Lead to reduced bonding reliability and damage to the package structure
At the same time, the delamination phenomenon will also destroy the electrical connection between the chip 13 and the external components, resulting in damage to the connection between the wire structure 14 and the chip 13 or between the wire structure 14 and the external components, resulting in a decrease in electrical reliability.

Method used

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  • Substrate for semiconductor package structure, semiconductor package structure and manufacturing method thereof
  • Substrate for semiconductor package structure, semiconductor package structure and manufacturing method thereof
  • Substrate for semiconductor package structure, semiconductor package structure and manufacturing method thereof

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Embodiment Construction

[0032] The following will illustrate the content of the present invention through embodiments, which relate to the semiconductor package structure with better bonding and the manufacturing method thereof. However, the embodiments of the present invention are not intended to limit the present invention to be implemented in any specific environment, application or special method as described in the embodiments. Therefore, the descriptions about the embodiments are only for the purpose of explaining the present invention rather than limiting the present invention. It should be noted that in the following embodiments and accompanying drawings, elements irrelevant to the present invention have been omitted and not shown, and the dimensional proportional relationship between the elements shown in the accompanying drawings is for the purpose of illustrating the embodiments, not the actual production of the elements. time limit.

[0033] Please refer to figure 2 , which shows a sch...

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PUM

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Abstract

The invention relates to a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises a baseplate, a junction layer and a chip. A concave part is formed on the baseplate to ensure that the concave part has thicker longitudinal dimension when the junction layer is coated on the baseplate. Therefore, the baseplate has the thicker junction layer when the junction layer is joined with the chip, and the invention provides more stable junction.

Description

technical field [0001] The invention relates to a semiconductor packaging structure and a manufacturing method thereof; in particular, to a semiconductor packaging structure capable of improving the bonding reliability of a chip and a substrate and a manufacturing method thereof. Background technique [0002] Advanced semiconductor packaging technologies have become more and more common, such as mini-BGA (ball-grid array) technology, FBGA (fine pitch BGA) technology and so on. In this type of packaging technology, a semiconductor chip is bonded to a substrate, or leadframe, through a bonding layer. Furthermore, the material of the bonding layer is usually a gel-like material. The packaging process first applies the bonding layer to the area on the substrate that is intended to be bonded to the semiconductor chip, then places the semiconductor chip on the bonding layer, and applies a pressure and temperature to the bonding layer. In the packaging structure, after the bonding...

Claims

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Application Information

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IPC IPC(8): H01L23/13H01L21/58
CPCH01L2224/73265H01L2224/48227
Inventor 陈有信林鸿村
Owner CHIPMOS TECH INC
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