Receiver with chip-level equalisation

A technology of receiver and equalizer, which is applied in the shaping network, electrical components, transmission system, etc. Effect

Inactive Publication Date: 2008-12-24
NXP BV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this is a very complex process and thus not easy to implement
Even if implemented, there may be problems with false detections, missed detections, and incorrectly estimated magnitudes
Furthermore, despreading is performed independently for each active code in each level of the OVSF tree, which leads to high computational complexity

Method used

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  • Receiver with chip-level equalisation
  • Receiver with chip-level equalisation
  • Receiver with chip-level equalisation

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Embodiment Construction

[0043] In the following, preferred embodiments will be described based on the HSDPA data access system according to the UMTS standard Release 5 specification. HSDPA has been developed to provide high speed data rates in the downlink direction. Due to this feature and due to the dispersion properties of the HSPDA channel, the traditional Rake receiver according to the above first method is no longer considered, while the equalizer scheme according to the above second method is considered as the key solution.

[0044] Fig. 1 shows a schematic block diagram of a receiver 10 in which the preferred embodiment of the invention may be implemented. The receiver 10 has an adaptive interference suppression algorithm based on channel equalization and adapted to synchronous CDMA systems using orthogonal spreading codes in a scrambling manner. In particular, the receiver 10 does not necessarily have any training sequence or training information for adaptive equalization. The receiver 10 ...

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Abstract

The present invention relates to receiver apparatuses and methods of controlling weight adaptation in a receiver of a code multiplex telecommunications system with orthogonal spreading codes, wherein received discrete time signal samples are chip-level filtered by using a first equalising step. Additionally, the received discrete time signal samples are delayed by a time period corresponding to a data symbol and used in a second equalising step. Symbol estimates obtained from the first equalising step are non-linearly filtered and used as a desired response for the second equalising step in the following symbol period, wherein equaliser weights adapted in the second equalising step are used for the first equalising step. Alternatively, the second equalising step may be dispensed with and weight adaptation may be incorporated in a single equalising step. As an additional or alternative option, a hybrid equaliser architecture may be provided, where the above two-step equalisation is used during an active phase where a channel is allocated, while another weight updating scheme is used during an inactive phase where no channel is assigned. Thereby, detrimental effects of interference power can be reduced at low increase in complexity.

Description

technical field [0001] The present invention relates to a receiver apparatus and method for controlling weight adaptation in a receiver of a code division multiplexing communication system using orthogonal spreading codes. As an example, the present invention relates to a receiver device and weight adaptation method for a High Speed ​​Downlink Packet Data Access (HSDPA) system introduced by the Universal Mobile Telecommunications System (UMTS) Release 5 standard. Background technique [0002] A Code Division Multiple Access (CDMA) system is based on a digital wideband spread spectrum technique in which multiple independent user signals are transmitted over an allocated available radio frequency band. In CDMA, each user signal includes a different orthogonal code and a pseudo-random binary sequence that modulates the carrier, thereby spreading the spectrum of the waveform, thereby allowing a large number of user signals to share the same spectrum. In the receiver, the user s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04B1/707H04J11/00H04L25/03H04B1/7105
Inventor 艾哈迈德·巴什图斯特凡尼·塞西亚
Owner NXP BV
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