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A decoding method for block low-density check code and reconstruction of multi-mode decoder

A low-density check code and low-density check technology, which is applied in the field of high-speed broadband wireless digital communication, can solve the problems of fixed data throughput, large storage resources, and no consideration of requirements, so as to improve data throughput and utilization rate , read and write access control simple effect

Inactive Publication Date: 2008-09-10
ZHEJIANG UNIV
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Problems solved by technology

For example, comparative literature: T. Zhang, "A 5 4Mbps(3, 6)-REGULAR FPGA LDPC DECODER", 2002, he gave a hardware decoder implementation of structured regular low-density check code, using Partially parallel structure, the external information of variable nodes and check nodes is completely preserved during the iteration process, the storage resources are relatively large, and the data throughput is fixed; comparative literature: Tejas Bhatt et al. of Nokia Corporation, "Pipelined Block-Serial Decoder Architecture for Structured LDPC Codes", they designed a high-performance serial decoder by using the iterative update algorithm of partial parallel scheduling, but they did not consider the receiver to the decoder in terms of multiple codeword lengths and multiple encoding rates requirements

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  • A decoding method for block low-density check code and reconstruction of multi-mode decoder
  • A decoding method for block low-density check code and reconstruction of multi-mode decoder
  • A decoding method for block low-density check code and reconstruction of multi-mode decoder

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Embodiment 1

[0059] Such as Figure 7 As shown, the 3 / 4 code rate block low-density parity check matrix in this embodiment.

[0060] In the embodiment, the check matrix information initialization module will set the low density check matrix information and the configurable parameters in the decoding process:

[0061] 1) The number of matrix row blocks is M=8, the number of column blocks is N=32, wherein the size of each sub-block is 256X256, and the element value is P i ;

[0062] 2) Set the maximum number of iterations of decoding ITER max =15; set the parallel factor Zf=32, then the variable node and check node message distributed memory block number is 32; The number of variable node message units is 32;

[0063] Set the variable node degree distribution vector as:

[0064] V → = [ 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,5,5,5,5,5,5,5,3,2,2,2,2,2,2,2,2 ] ;

[0065] Set the check node degree di...

Embodiment 2

[0091] Such as Figure 9 As shown, the 1 / 2 code rate block low-density parity check matrix in this embodiment.

[0092] In the embodiment, the check matrix information initialization module will set the low density check matrix information and the configurable parameters in the decoding process:

[0093] 1) The number of matrix row blocks is M=16, the number of column blocks is N=32, wherein each sub-block size is 256X256, and the element value is P i ;

[0094] 2) Set the maximum number of iterations of decoding ITER max =15; set the parallel factor Zf=64, then the variable node and check node message distributed memory block number is 64, the size of the real-time cycle permutation network is 64, and the number of stages is 6; the check node and check node working in parallel The number of variable node message units is 64;

[0095] Set the variable node degree distribution vector as:

[0096] V → = [ 3...

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Abstract

The invention discloses a decoding method for a blocky check code with low density and a multi-mode reconfigurable decoder, and particularly relates to a decoding design based on the blocky check array of a unit cycle permutation array; the decoding method adopts partly collateral minimum and bias iterative compensation algorithm, and is characterized by low complexity and fast iterative convergence; the decoder has flexible configuration and high availability of resources, and the decoder is characterized in that: firstly, the decoder can support the blocky check array decoding with different code lengths under various code rates; secondly, the decoder can select and configure different messages to update concurrent factors according to the decoding delay and the throughput requirements; thirdly, node messages are stored in a distribution type, the write / read access control is easy, and the node messages are stored in a compression type, thereby effectively improving the utilitization of the stored resources; lastly, the iterative update adopts multi-level production line structure, thus fully improving the data throughput of the decoder. The method and the device of the invention have the advantages of stable performance, flexible configuration and good expansibility, etc.

Description

technical field [0001] The invention relates to the field of high-speed broadband wireless digital communication, in particular to a decoding method of a block low-density check code and a reconfigurable multi-mode decoder. Background technique [0002] Compared with Turbo codes, LDPC has the advantages of error correction performance close to Shannon's limit, low error floor, high decoding parallelism and low delay, and is especially suitable for high-speed broadband wireless digital communication systems to ensure data reliable and efficient transmission. At present, LDPC has been applied in many fields: the second-generation satellite digital TV video broadcasting standard (DVB-S2) adopts LDPC as the core channel coding technology; 802.16e and 802.11n two international standards adopt Low density check code is used as a supplementary channel coding scheme; my country's digital TV terrestrial transmission standard and mobile phone mobile TV standard both use low density ch...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11H04L1/00
Inventor 赵民建李旻杨丽萍雷鸣赵辉沈文丽周侨李磊
Owner ZHEJIANG UNIV
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