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Decoding method of LDPC code based on parity check matrix and decoder thereof

A technology of parity check matrix and LDPC code, which is applied to the application of error detection coding of multi-bit parity, error correction/detection using block code, digital transmission system, etc., which can solve the problem of resource consumption and low decoding efficiency. Satisfactory and other issues, to achieve the effect of increased decoding rate and reduced scale of hardware resources

Inactive Publication Date: 2008-07-30
BEIHANG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This document proposes a partially parallel decoder and decoding method that is currently common in the field, but it is more suitable for regular codes, and has special requirements for the row weight and column weight of the supervisory matrix, so this The decoding scheme is still unsatisfactory in terms of decoding efficiency for irregular codes, and for LDPC codes with long code length and large matrix size, there is still a resource-consuming bottleneck

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  • Decoding method of LDPC code based on parity check matrix and decoder thereof
  • Decoding method of LDPC code based on parity check matrix and decoder thereof
  • Decoding method of LDPC code based on parity check matrix and decoder thereof

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Experimental program
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Embodiment 1

[0041] First narrate the division method of a kind of parity check matrix of the present invention

[0042] FIG. 1 is a splitting method for performing parity splitting on a parity check matrix (hereinafter referred to as "H matrix") used in LDPC decoding.

[0043] The odd-even split method in Figure 1 divides the H matrix into two matrices, namely H 0 Matrix and H 1 matrix. The specific division method is to mark the column in the H matrix as the sub-matrix column of 0 (A 00 A 10 …A q0 ) T drawn as H 0 The first submatrix column of the matrix, the submatrix column that marks the column in the H matrix as 1 (A 01 A 11 …A q1 ) T drawn as H 1 The first sub-matrix column of the matrix; follow the same method, sequentially extract the sub-matrix columns in the H matrix and put them into H alternately 0 Matrix and H 1 Matrix, the above sub-matrix columns follow the original order in the H matrix, respectively in the new matrix H 0 and H 1 sorted in. Thus, for H af...

Embodiment 2

[0127] On the basis of the CNU unit structure of the decoder described in Embodiment 1, a unit for calculating H×x=0 is added. Specifically, while keeping the structure of the CNU unit in Embodiment 2 unchanged, s XOR units are added, arranged as in the arrangement structure of z XOR units in Embodiment 2 of the original CNU, the purpose is to input The x+1 one-bit information of the CNU is XORed, and a one-bit XOR result is output.

[0128] According to the modification of the structure of the CNU unit in Embodiment 1 in Embodiment 2, certain adjustments need to be made to the control of the controller unit 0 of the decoder, that is, in the embodiment that maintains the decoding steps of the decoder? In the case of the same timing, while the CNU operation of the next iteration cycle is performed, the x calculated for the previous iteration cycle n , carry out the calculation of H×x=0, if the equation is established, the controller unit 0 will issue an instruction to stop the...

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Abstract

The invention provides a LDPC interpretation method and an encoder based on the matrix splitting on a parity-check matrix. Firstly, the matrix is split; based on the single new matrix after splitting, a check node renewing unit (CNU) and a variable node renewing unit (VNU) are deployed, and a check node renewing calculation and a variable node renewing calculation are arranged, so as to renew check node information and variable node information of the whole original parity-check matrix after intermediate information of each new matrix is calculated respectively, and the above mentioned steps are repeated for iteration until the decoding succeeds or the steps are ended when reaching the maximum iteration times. By adopting the interpretation method and the encoder provided by the invention to decode the LDPC code, compared with the decoding proposal before the matrix splitting, the scale of the hardware source approximately reduces one third at the same decoding speed when splitting according to a parity method; the decoding speed is approximately increased by one third under the same hardware source.

Description

technical field [0001] The invention belongs to the communication field, and in particular relates to a decoding method and a decoder. Background technique [0002] LDPC code, full name Low Density Parity Check Code, that is, low density parity check code. Among the currently existing encoding methods, the encoding method of LDPC code has shown the encoding performance close to Shannon's limit; in terms of decoding, compared with the Turbo code which is also a long code, the bit error of LDPC code is The error floor appears in a very low bit error rate area, and the probability that the error codeword cannot be detected is an extremely low value very close to 0; the parity check matrix H of the LDPC code is a sparse matrix, which is " The origin of the name "low density", and this feature enables it to be decoded by a simple and easy-to-implement decoding method, which has extremely high practical value. Due to the above reasons, LDPC has become a hot spot in research and ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11H04L1/00
Inventor 张晓林赵岭张展苏琳琳
Owner BEIHANG UNIV
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