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Maximum likelihood detector, error correction circuit and medium storage device

A maximum likelihood and error correction technology, applied in the field of maximum likelihood detectors, which can solve the problems of large circuit scale, data string failure, and inability to improve correction performance.

Active Publication Date: 2008-05-07
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the generation of candidate data strings by the maximum likelihood detector is inadequate, ECC decoding may fail for all candidate data strings and the correction performance cannot be improved
[0034] If a maximum likelihood detector is provided for all candidates, the candidate sequence must be sorted and transmitted to the ECC decoder in the order of lower likelihood, so the calculation amount for generating the candidate data string increases, and the circuit scale get bigger

Method used

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  • Maximum likelihood detector, error correction circuit and medium storage device
  • Maximum likelihood detector, error correction circuit and medium storage device
  • Maximum likelihood detector, error correction circuit and medium storage device

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Embodiment approach

[0198] In the above-described embodiment, two error candidates are selected in each likelihood level, but one or three or more error candidates may also be selected. The structure of the ECC decoder is not limited to the structure shown in FIG. 5 , and other structures can be used. In addition, the above describes the case of a recording / reproducing device using a magnetic disk device, but the present invention can be applied to other medium storage devices such as optical disc devices and other communication devices.

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Abstract

The present invention provides a maximum likelihood decoder, error correction circuit and a medium storage device. The maximum likelihood decoder creates a decoding target data string and provides error candidates that are effective for an error correction circuit. The decoder has a detector for creating a decoding target data string, and an error candidate extractor for extracting the bit positions of which likelihood of each bit shows a high probability of error as the error candidates of the decoding target data string based on the likelihood information from the detector. Since only the bit positions of which error probability is high are extracted as error candidates, a correction circuit can extract the error candidates in the sequence of the lower likelihood, and the number of times of sorting in the sequence of likelihood can be decreased.

Description

technical field [0001] The present invention relates to a maximum likelihood detector, an error correction circuit, and a medium storage device, and more particularly, the present invention relates to a maximum likelihood detector, an error correction circuit, and a medium for correcting errors of data appended with an ECC code storage device. Background technique [0002] In the fields of recording / reproducing devices (for example, magnetic disk devices) and communication systems, Reed Solomon codes are used as error correction codes (ECC). In order to improve data reproduction reliability when reproducing data from low-quality transmission signals and recording / reproducing signals, data decoding techniques using maximum likelihood sequence detection and error correction techniques using error correction codes (ECC) are widely used. [0003] Because of the influence of medium noise and circuit noise, the bit string output from the maximum likelihood detector has erroneous ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/00H03M13/29G11B20/10G11B20/18
CPCH03M13/45H03M13/455H03M13/453H03M13/1575H03M13/1545G11B2220/90H03M13/6343H03M13/451H03M13/15G11B2020/1836G11B20/10009H03M13/1535G11B20/1803H03M13/153H03M13/37
Inventor 伊东利雄
Owner FUJITSU LTD
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