Method for reducing stray capacitance in analogue circuit

Abstract

The invention relates to a method for reducing the parasitic capacitance in analog circuit, which comprises the following steps: an insulation layer is grown on the semiconductor substrate; then a signal line is prepared on the insulation layer, wherein, an N well layer is introduced before growing the insulation layer and is arranged between the insulation layer and the semiconductor substrate. The invention has the advantages that the parasitic capacitance is reduced without increasing the layout area simultaneously, that is, the parasitic capacitance of signal is reduced without increasing the circuit cost.

Description

technical field [0001] The invention relates to the field of analog circuit layout design, in particular to a method for reducing parasitic capacitance in an analog circuit. Background technique [0002] The invention is mainly applied in the layout design of analog integrated circuits and in the realization of semiconductor devices. In the process of physical realization of analog circuits, the parasitic capacitance devices on some signal lines usually greatly affect the performance of the circuit, especially for some sensitive high-frequency signals, the influence of parasitic capacitance is more obvious. The parasitic capacitance on the signal line will increase the load, reduce the operating frequency and narrow the operating bandwidth, and will be coupled to the signal line, degrading the anti-interference ability of the signal. Traditional design methods such as figure 1 shown. A layer of insulating layer 2 is grown on the P-type substrate 1, above which is the sign...

AI Technical Summary

Problems solved by technology

The problem caused by reducing A is that the parasitic resistance on the signal line 3 is increased, and the current channel is reduced, which indirectly causes the speed of the circuit to slow down.

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