Plasma etching method and device

Abstract

The invention discloses a plasma etching method and device, wherein, the method includes the following steps: the inside of a reaction chamber is provided with a semiconductor substrate which is provided with a to-be-etched material layer; etching gas which is ionized into plasma by a radio frequency power source is fed in the reaction chamber; the radio frequency power source outputs radio frequency power in pulse output mode. The device comprises a reaction chamber, a wafer holder, a first radio frequency power source, a loop winding, a second radio frequency power source and a pulse control circuit, wherein, the inside of the reaction chamber contains the etching gas; the wafer holder is used to bear the weight of a semiconductor wafer; the first radio frequency power source provides bias voltage for the wafer; the loop winding is arranged at the upper part and the top of the reaction chamber; the second radio frequency power source which is used to generate radio frequency power is connected with the loop winding through the pulse control circuit and outputs radio frequency power in pulse output mode to ionize the etching gas into plasma. The invention can generate plasma which is output in pulse mode and used for etching, thereby improving the control precision of etch end point.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a plasma etching method and a plasma etching device in the manufacturing process of semiconductor devices. Background technique [0002] With the rapid development of semiconductor manufacturing technology, integrated circuits tend to have faster computing speed, larger data storage capacity and more functions. Semiconductor wafers are moving towards higher component density and higher integration. The feature size of the gate line width of semiconductor devices such as MOS (Metal Oxide Semiconductor) devices is getting thinner and shorter than before. [0003] The manufacturing process of a metal oxide semiconductor device starts with forming an insulating layer, such as a silicon oxide film and a silicon nitride film, on a silicon substrate. The insulating layer is patterned and an opening is formed on the insulating layer through photol...

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Problems solved by technology

However, for devices with a thickness of 65nm and below, the thickness of the gate oxide layer is only about 10 Ȧ. The above-mentioned depressions caused by the loss of silicon will make it difficult to control the depth of the LDD region, seriously affecting device performance.

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