Apparatus and related method for detecting phase of input data

Abstract

An apparatus for detecting a phase of an input signal includes: a phase detector unit for detecting the phase of the input signal referring to a plurality of clock signals having different phases and for outputting a plurality of phase detection results, wherein each of the phase detection results represents a candidate phase of the input signal and corresponds to one of the clock signals; and a phase decision unit, coupled to the phase detector unit, for determining the phase of the input signal according to the phase detection results.

Description

technical field [0001] The present invention relates to a device for detecting a phase of an input signal and its related method, especially to a device using a delay-locked loop (Delay-Locked Loop, DLL) circuit to detect the phase of an input signal and the method thereof. Related method (APPARATUS AND RELATED METHODFOR DETECTING PHASE OF INPUT DATA). Background technique [0002] Many high-speed serial interfaces (such as Universal Serial Bus (Universal Serial Bus, USB) 2.0 or high-definition multimedia interface (High-definition Multimedia Interface, HDMI)) have become more and more popular as interfaces for transmitting data. Generally speaking, a traditional delay-locked loop (DLL) circuit is used to select clock pulses and data from an input sequence of data, so when designing a delay-locked loop circuit, some number of delayed clock pulse signals will be used to sample the Input data to detect the phase of the data, in addition, the delay locked loop circuit will sel...

AI Technical Summary

Problems solved by technology

[0003] However, due to signal jitter interference, the phase of the input data may shift frequently, so the existing delay-locked loop circuit will lock the specific clock signal to become the There will be great difficulty in recovering the clock pulse. In addition, the existing delay-locked loop circuit may also lock to the wrong clock signal to recover the data. In this way, the input data recovered from the recovered clock signal may The set time or hold time required to violate the edge of the reply data

Therefore, the data returned by the existing delay-locked loop circuit may be wrong. In addition, the operation time required for the existing delay-locked loop circuit to lock the phase of the input data is unpredictable.

To sum up, the existing delay-locked loop circuit not only has a lot of problems in design, but also has instability. The most critical part of the phase-locked loop circuit

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