Non volatile memory device and its operation method

Abstract

The invention discloses a nonvolatile memory with the page buffer provided with two resisters, and the memory comprises a memory unit matrix, a selector circuit and a page buffer circuit. The selector circuit is coupled with an outer data bus, the page buffer circuit comprising a first resister and a second resister is coupled between the memory unit matrix and the selector circuit, and the firstand the second registers are coupled together via a sensing node. The first and the second registers alternately write the data into the memory unit matrix through programming. When programmed write is carried out for one of the first and the second resisters, the other register is used for storing the data from the data bus at the same time. In other words, when programmed write is being carriedout by the first resister, the second memory is used for storing the data from the data bus, and when programmed write is being carried out by the second resister, the first memory is used for storing the data from the data bus.

Description

technical field [0001] The present invention relates to a semiconductor memory device, in particular to a non-volatile memory device with a page buffer circuit having a dual register and an operating method thereof. Background technique [0002] U.S. Patent No. 6,671,204 entitled "Non-Volatile Memory Device with Dual Registers in Page Buffer and Method of Operation Thereof" describes a cache program and copy-back ) function of the page buffer design. FIG. 1 is a schematic diagram illustrating a page register and sense amplifier block 120 . The page register and sense amplifier block 120 is coupled between a memory cell array 110 and a Y gate control circuit 130 . The page register and sense amplifier block 120 includes a bit line control circuit 140 and a page buffer 122 . The page buffer 122 has a sense line 125 connected to the bit line control circuit 140 via a sense node E. As shown in FIG. [0003] The bit line control circuit 140 includes four NMOS transistors 141 ...

AI Technical Summary

Problems solved by technology

Because data must be transferred between the main register 150 and the auxiliary register 170, the programming and writing procedure thereof is relatively complicated, and data transfer between the two registers also takes more time.

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