Delay locked loop circuit and method for provding delay locked loop clock of synchronous memory device

Abstract

A synchronous memory device having a normal mode and a power down mode includes a power down mode controller for generating a power down mode control signal in response to a clock enable signal, thereby determining onset or termination of a power down mode. A clock buffering unit buffers an external clock signal in response to the power down mode control signal and outputs first and second internal clock signals. A clock selection unit selects one of the first and second internal clock signals based on the power down mode control signal to output the selected signal as an intermediate output clock signal. A phase update unit performs a phase update operation by using the intermediate output clock signal to output a delay locked loop (DLL) clock signal, the first internal clock signal differing in frequency from the second internal clock signal.

Description

technical field [0001] The present invention relates to a delay locked loop (DLL) circuit of a synchronous DRAM, and more particularly, the present invention relates to a DLL circuit performing stable operation in a power saving mode for low power operation of a semiconductor device. Background technique [0002] A synchronous semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) performs data transfer with an external device using an internal clock signal synchronously locked to an external clock signal input from an external device such as a memory controller. In order to transmit data stably, the data should be precisely positioned at the edge or center of the clock by compensating for delay time inevitably caused by a time difference between data transmission of each component and data loaded into the bus. [0003] The clock synchronization circuit used to compensate the delay time is a phase-locked loop (PLL) or a delay-locked loop (DLL). ...

AI Technical Summary

Problems solved by technology

As a result, it is difficult to accurately transfer data to / receive data from DRAM because the phase of the external clock signal is different from that of the DLL clock signal DLL_CLK of the DLL circuit

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