Network-on-chip digital router and its parallel data transmission method

Abstract

The utility model relates to a network-on-chip digital router and a parallel data transmission method thereof, also known as the digital universal joint, pertaining to the field of the large scale integration. The network-on-chip parallel digital router is characterized in that a FIFO traveling wave shift buffer storage, a co-gradient matrices switch array, a route decision module and a parallel network port are gathered on the chips. Such method is different with the traditional network parallel data transmission. The utility model has the advantages that 1. The data transmission jam is not caused due to the increase of on-chip-bus with the processor. 2. The network parallel data transmission method improves the message transmission rate and reduces the time and resources needed for the conversion between parallel and serial data, so as to accelerate the data communication rate among the processors and increase the interoperability of a plurality of processors.

Description

(1) Technical field [0001] The invention relates to an on-chip network digital router and a parallel data transmission method thereof, belonging to the technical field of large-scale integrated circuit design. (2) Background technology [0002] With the advancement of integrated circuit technology, tens of millions of gate circuits can be integrated on a single chip under the condition of deep submicron technology. On such a complex VLSI chip, multiple processors can be integrated to form a system chip. Many large-scale integrated circuit design and manufacturing companies in the world generally use the on-chip bus structure for data transmission between on-chip multi-processors. However, research on data transmission methods between on-chip multi-processors by international integrated circuit research institutions and colleges and universities shows that, when the number of on-chip processors is large, the performance of the network structure is superior to that of the bus...

AI Technical Summary

Problems solved by technology

[0004] The disadvantages of the on-chip bus structure are: when the number of on-chip processors increases, the competition for bus resources intensifies, resulting in data congestion; the time delay formed by the longer connection causes circuit dysfunction; the disadvantages of the traditional on-chip network structure are: The network protocol is relatively complicated, which increases the consumption of the chip area, and the serial data transmission method cannot give full play to the functional advantages of the system chip

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