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Semiconductor device having a frontside contact and vertical trench isolation and method of fabricating same

A trench isolation and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as interfering with the performance of adjacent devices

Inactive Publication Date: 2009-08-05
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Said crosstalk occurs as a result of applied voltages in active devices causing potential fluctuations through horizontal dielectric isolation; thus disturbing the performance of adjacent devices

Method used

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  • Semiconductor device having a frontside contact and vertical trench isolation and method of fabricating same
  • Semiconductor device having a frontside contact and vertical trench isolation and method of fabricating same
  • Semiconductor device having a frontside contact and vertical trench isolation and method of fabricating same

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Embodiment Construction

[0035] The following reference Figure 4 , Figures 4a-4f and Figure 5 , to describe in detail the fabrication method of the device according to the exemplary embodiment of the present invention.

[0036] step 100

[0037] consider as Figure 4 A silicon-on-insulator substrate 20 is shown, wherein the bottom substrate layer 2 is composed of silicon, and the insulating layer 4 is composed of silicon dioxide (SiO 2 ) composition, and the active semiconductor layer 6 is composed of silicon. In the first step, a field-induced oxide layer is grown on the exposed surface of the active semiconductor layer 6 of the substrate 20 by an oxidation process, the layer comprising silicon dioxide (SiO 2 ) layer 22, the oxidation process is well known to those of ordinary skill in the art. The purpose of the field oxide layer is to protect the active layer 6 of the substrate 20 and to form doped carriers. A subsequent nitridation step may also be performed to form a nitride (Si 3 N 4...

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Abstract

A method of forming a contact stud (36) and surrounding isolation trench (28) in a semiconductor-on-insulator (SOI) substrate (20). The method comprises: etching a contact hole (26) and a surrounding isolation trench (28) from an active layer (6) of a substrate (20) to an insulating layer (4); performing a mask on the trench (28), The contact hole (26) is then further etched into the bottom substrate layer (2); the trench (28) and the contact hole (26) are filled with undoped intrinsic polysilicon (34); and the contact hole (26) is then filled The polysilicon material is subjected to a doping process to form an in-situ highly doped contact column (36), while the material filling the trench (28) remains non-conductive. The method can simultaneously form the isolation trench and the contact column, thereby avoiding undue disturbance of the device manufacturing process.

Description

technical field [0001] In general, the present invention relates to semiconductor devices with front-side contact and vertical trench isolation, and in particular, the present invention relates to an active semiconductor device with respect to a semiconductor-on-insulator (SOI—semiconductor-on-insulator) substrate Areas form contact pillars and separate trenches. Background technique [0002] Often, especially in high voltage applications, it is desirable to completely electrically isolate active semiconductor devices from the underlying semiconductor substrate ("vertical" isolation) and adjacent active devices ("horizontal" isolation). [0003] Vertical isolation of active devices is generally achieved by using a semiconductor-on-insulator (SOI) substrate, see figure 1 The SOI substrate shown comprises: a base semiconductor (usually silicon) substrate 2 with a buried insulator (usually silicon oxide) layer 4 formed on its upper surface; and an active bonding semiconductor ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/74H01L27/12
CPCH01L21/76283H01L21/84H01L27/1203H01L21/743H01L21/74H01L21/20H01L27/12
Inventor 沃尔夫岗·劳舍尔
Owner NXP BV
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