On-chip system

Abstract

The on-chip system includes several functional modules connected with internal bus including two independent transmission channels, including one control / state channel for transmitting control / state information and one data channel for transmitting other data except control / state information. Each of the control / state channel and the data channel has separate data bus, address bus and control bus. The kernel of the present invention is to design on-chip system bus in the strategy of separate control / state channel and data channel, which have different topologic structures and communication protocols. The present invention has greatly simplified interface design of functional modules inside the system and increased total system communication bandwidth, and is especially suitable for on-chip system design with compact data interaction.

Description

technical field [0001] The present invention relates to the field of semiconductor chips, and more specifically, relates to a system on chip. Background technique [0002] With the development of semiconductor technology level to deep submicron and the further improvement of EDA tools, more and more complex functional modules (usually IP modules) can be integrated inside the chip to form a complex system-on-a-chip (System-on-a- chip, SoC). In general, a large amount of data needs to be exchanged between various functional modules, and these data exchanges are completed by communication links, so the communication link often becomes the bottleneck of system performance. According to whether the functional modules share the communication link, the communication link can be divided into a point-to-point mode and a bus mode. If each functional module within the system is connected by a shared communication link, the system architecture is based on the bus. Each functional mod...

AI Technical Summary

Problems solved by technology

The bandwidth of the data bus is the maximum communication bandwidth of the entire system. If the control\status information and other data are transmitted using the same data bus, the various functional modules in the system need to exchange data frequently. When the maximum communication bandwidth required by the entire system exceeds the bandwidth of the data bus, the internal bus becomes the communication bottleneck

Especially when multiple functional modules compete for the same bus resource, the central arbitrator will only allow one functional module to use the resource at a time, and other functional modules must wait, and some functional modules need to wait for a long time to obtain the right to use the bus , the insertion of a large number of waiting cycles will prolong the running time of the system and greatly reduce the performance of the system

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