Software and hardware synergistic simulation/ validation system and vector mode simulation/ validation method

Abstract

The system with a PC software part and FPGA hardware comprises: a bottom layer to transfer information on physical channel, a middle layer to pack and unpack data frame, and a top layer for signal input / output. Wherein, it sends ahead the expected result into the hardware for storage. This invention improves simulation speed greatly with well accuracy.

Description

technical field [0001] The invention discloses a software-hardware co-simulation / verification method in vector mode, which belongs to the technical field of SoC simulation and verification. Background technique [0002] Terminology and some important abbreviations [0003] Software-hardware co-simulation / verification: refers to dividing a large-scale simulation / verification system into two parts, software and hardware, and the part that requires a lot of calculations is simulated / verified on the FPGA hardware platform, which is called the hardware part; The stage description or the simulation / verification part for stimulus input and response output is done using PC or workstation, which is called software part. In this way, a large-scale simulation / verification system with improved functions and speed can be formed by combining the respective advantages of FPGA hardware simulation and PC software simulation. [0004] Vector software-hardware co-simulation / verification mode...

AI Technical Summary

Problems solved by technology

Because there are so many powerful modules and there are complex interaction processes between these modules, the difficulty of SoC system design is increasing rapidly, and simulation / verification is the most important part of the integrated circuit design process. The complexity is also growing rapidly, which makes the traditional method far from meeting the needs of the current industry

The main problem facing the current SoC system simulation / verification field is that a large number of software simulations are required, and a large number of experiments show that in the design process, when more than one million clock cycles are required to fully test and verify the SoC system functionality , the performance of the software simulation simulator will drop to 1~5Hz, which will inevitably lead to a sharp increase in test time and error probability

However, no matter which of the above methods is adopted, the efficiency will inevitably be reduced.

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