Low-voltage conrol method and device

Abstract

A semiconductor device for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and circuitry for controlling the timing of turning on / off the plurality of voltage generators upon entry / exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level.

Description

[0001] cross-reference [0002] This application is the priority document of Provisional Application Serial No. 60 / 287,249, filed April 27,2001. This disclosure is hereby incorporated by reference in its entirety. [0003] This application involves the jointly assigned patent application serial number ____ (abstract number: 8729-212) technical field [0004] The present invention relates to an internal voltage control method and device in a semiconductor memory device, and more particularly to a method and device that reliably operates a volatile semiconductor memory and reduces ) surge through the internal circuits in the volatile semiconductor memory. Background technique [0005] A longstanding goal for semiconductor memory designers has been to design higher cell density and faster semiconductor memories that consume less power. Since dynamic random access memory (DRAM) has a smaller cell size than sta...

AI Technical Summary

Problems solved by technology

Large electrical surges cause severe strain on the battery, generating heat and potentially disabling circuits

In addition, some nodes in the circuit that are turned off may drift to unspecified voltages, and if the circuit is not properly turned on, false triggering of the internal circuits of the DRAM may also occur

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