Low power clock distribution scheme

Abstract

An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the select / deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

Description

PRIORITYThis application claims priority from Indian patent application No. 431 / Del / 2002, filed Apr. 5, 2002, which is incorporated herein by reference.FIELD OF THE INVENTIONThe invention relates generally to clock distribution in electronic circuits. In particular, the invention relates to reduction of power consumption by selective enabling of clock signals.BACKGROUND OF THE INVENTIONA vast majority of digital electronic circuits include synchronous sequential logic circuits that require a clock signal for their operations. One or more clock signals are distributed to every part of the circuit containing such synchronous sequential logic circuits. For large circuits, it is a general practice to organize the clock distribution as a hierarchical arrangement in the form of a “clock tree” that distributes the clock over the entire circuit.The power consumption of an electronic circuit is largely dependant on the switching of the logic circuits in response to the clock signal because t...

AI Technical Summary

Benefits of technology

An embodiment of the invention provides an improved clock distribution architecture that reduces power consumption and provides a mechanism that implements the selection or deselection of the clock signals automatically based on circuit operation.

As such, one embodiment of the invention provides, in an electronic circuit containing one or more digital synchronous sequential logic blocks, at least one of which is either selected or deselected during operation, an improved clock distribution scheme that reduces power consumption, comprising: identifying means for determining the select / deselect state of each said deselectable synchronous, sequential-logic block, coupled to disabling means for disabling the clock input to each deselected synchronous, sequential logic block.

An embodiment of the present invention further provides in a programmable logic device containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation, an improved clock distribution scheme that reduces power consumption, comprising: identifying means for determining the select / deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

Another embodiment of the invention provides in a programmable gate array (PGA) containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation, an improved clock distribution scheme that reduces power consumption, comprising: identifying means for determining the select / deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

Another embodiment of the present invention provides a method for reducing power consumption in an electronic circuit containing one or more digital synchronous sequential logic blocks at least one or which is either selected or deselected during operation, comprising the steps of: identifying the select / deselect state of each deselectable logic block, and disabling the clock input to each deselected logic block.

Problems solved by technology

The power consumption of an electronic circuit is largely dependant on the switching of the logic circuits in response to the clock signal because the static power consumption, especially for CMOS circuits that are widely used in electronic devices, is extremely low.

The predominant dynamic power consumption is the result of charging and discharging of internal and external capacitors.

Increased power dissipation also results in reduced reliability as the circuit components operate at a higher temperature.

The increased power dissipation may also require the use of expensive packaging and / or heat dissipation arrangements to manage the heat generated, thereby resulting in increased cost.

This scheme results in wasted power.

In the case of FPGAs, this inefficiency can result in limitations on gate density and / or maximum clock speed.

This results in a process that is relatively complex and inefficient to control the clock tree.

Images