Decoding method, memory storage device and memory control circuit unit

a decoding method and memory storage technology, applied in the field of decoding technology, can solve problems such as the increase of the probability of decoding failure, and achieve the effect of improving the decoding efficiency

Active Publication Date: 2018-10-11
PHISON ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0006]The invention is directed to a decoding method, a memory storage device and a memory control circuit unit, which are capable of improving a decoding efficiency.

Problems solved by technology

However, based on the existing error checking and correction mechanism, it is not easy to locate errors of specific types (e.g., errors caused by repeatedly writing or moving data in the rewritable non-volatile memory module), and thus a probability of decoding failure increases.

Method used

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  • Decoding method, memory storage device and memory control circuit unit
  • Decoding method, memory storage device and memory control circuit unit
  • Decoding method, memory storage device and memory control circuit unit

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Embodiment Construction

[0030]Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0031]Embodiments of the present invention may comprise any one or more of the novel features described herein, including in the Detailed Description, and / or shown in the drawings. As used herein, “at least one”, “one or more”, and “and / or” are open-ended expressions that are both conjunctive and disjunctive in operation. For example, each of the expressions “at least on of A, B and C”, “at least one of A, B, or C”, “one or more of A, B, and C”, “one or more of A, B, or C” and “A, B, and / or C” means A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B and C together.

[0032]It is to be noted that the term “a” or “an” entity refers to one or more of that entity. As su...

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PUM

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Abstract

A decoding method, a memory storage device and a memory control circuit unit. The method includes: reading a plurality of bits from a plurality of first memory cells; performing a first decoding operation on the bits according to first reliability information; and performing a second decoding operation on the bits according to second reliability information if the first decoding operation fails and meets a default condition, and the second reliability information is different from the first reliability information, and a correction ability of the second reliability information for a first type error of the bits is higher than a correction ability of the first reliability information for the first type error. In addition, the first type error is generated by performing a specific programming operation on the first memory cells based on error data.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Taiwan application serial no. 106111497, filed on Apr. 6, 2017. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.BACKGROUNDTechnical Field[0002]The invention relates to a decoding technology, and more particularly, to a decoding method, a memory storage device and a memory control circuit unit.Description of Related Art[0003]The markets of digital cameras, cellular phones, and MP3 players have expanded rapidly in recent years, resulting in escalated demand for storage media by consumers. The characteristics of data non-volatility, low power consumption, and compact size make a rewritable non-volatile memory module (e.g., flash memory) ideal to be built in the portable multi-media devices as cited above.[0004]There are various memory controllers configured with an error checking and correcting circuit. The e...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F11/10G06F3/06G11C29/52
CPCG06F11/1068G06F3/0619G11C29/52G06F3/0679G06F3/0659G06F11/1072G11C2029/0411
Inventor LIN, YU-HSIANGYEN, SHAO-WEIYANG, CHENG-CHELAI, KUO-HSIN
Owner PHISON ELECTRONICS
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