Stacked fan-out package structure

Abstract

A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Application No. 62 / 237,226 filed on Oct. 5, 2015 and U.S. Provisional Application No. 62 / 237,250 filed on Oct. 5, 2015, the entirety of which are incorporated by reference herein.BACKGROUND OF THE INVENTION[0002]Field of the Invention[0003]The present invention relates to a semiconductor package structure, and in particular to a stacked fan-out package structure with high reliability.[0004]Description of the Related Art[0005]In recent years, as electronic products have been become increasingly multifunctional and have been scaled down in size, there is a desire for manufactures of semiconductor devices to make more devices formed on a single semiconductor wafer, so that the electronic products including these devices can be made more compact. Responses to this desire have been the development of the Package-on-package (PoP) technique and wafer level package (WLP) technique. The PoP t...

AI Technical Summary

Benefits of technology

The patent text describes a new technique for protecting the sidewalls of interconnected semiconductor dies in a structure. A protective layer made of molding compound is applied to prevent damage caused by poor moisture resistance. This layer is formed without any additional process and prevents delamination between the semiconductor die and the interconnect structure, improving reliability and yield. Additionally, the technique helps increase the throughput of the overall semiconductor package structure.

Problems solved by technology

However, some problems may occur while manufacturing the semiconductor package utilizing the PoP and / or WLP techniques.

As a result, the RDL structure may be damaged easily due to poor moisture resistance.

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