Polishing apparatus

Abstract

A polishing apparatus capable of performing multi-stage polishing of a substrate, such as wafer, is disclosed. The polishing apparatus includes: a plurality of polishing tables each for supporting a polishing pad; a plurality of polishing heads each configured to press a substrate against the polishing pad; and a transporting device configured to transport the substrate to at least two of the plurality of polishing heads. The plurality of polishing heads have different structures.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This document is a Divisional application of U.S. patent Ser. No. 14 / 672,003 filed Mar. 27, 2015, which claims priorities to Japanese Patent Application Number 2014-072965 filed Mar. 31, 2014 and Japanese Patent Application Number 2014-229169 filed Nov. 11, 2014, the entire contents of which are hereby incorporated by reference.BACKGROUND[0002]As semiconductor devices have been in a trend toward high integration and high density in recent years, circuit interconnects are also becoming smaller and finer, and the larger number of layers are used to form multilayer interconnects. The multilayer interconnects with the finer circuits entail greater surface steps which reflect surface irregularities of lower layers. An increase in the number of interconnect layers would result in poor film formation (or step coverage) over stepped configurations of thin films. Therefore, better multilayer interconnects need to have the improved step coverage an...

AI Technical Summary

Benefits of technology

This patent describes a polishing apparatus that can perform multistage polishing of a substrate, such as a wafer. The apparatus includes multiple polishing heads with different structures and arrangements, which can provide better control and precision in shaping the substrate's profile. The use of different polishing heads can also reduce maintenance costs and facilitate the use of different types of polishing pads for different stages of polishing. Additionally, the apparatus can use different elastic membrane shapes and retainer ring widths to achieve different polishing results. Overall, the patent provides a cost-effective solution for achieving optimal polishing of substrates.

Problems solved by technology

An increase in the number of interconnect layers would result in poor film formation (or step coverage) over stepped configurations of thin films.

Furthermore, miniaturization of a photolithographic process necessitates a smaller depth of focus in a photolithographic optical system, and therefore a surface of the semiconductor device needs to be planarized such that the irregularities or steps on the surface of the semiconductor device will fall within the depth of focus.

However, such a high-performance polishing head has a complicated structure and has costly consumables (the membrane, the retainer ring, etc.), and therefore entails an increased maintenance cost and an increased running cost.

Further, a frequency of maintenance work will also increase, resulting in a decrease in an operation rate of the apparatus.

However, the polishing head of this type cannot control the polishing rate in smaller areas than the pressure chambers.

It is possible to perform finer control of a wafer profile by using more pressure chambers, but there is a limit on the number of pressure chambers that can be provided in the polishing head.

Furthermore, the above-described polishing head is not able to positively control a polishing rate of a wafer at a boundary between the pressure chambers, and therefore the polishing rate may be low at the boundary between the pressure chambers.

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