Systems and methods for transition-minimized data bus inversion

Abstract

Circuits and methods for Data Bus Inversion (DBI) are provided. In one example, the immediately previous value of the DBI bit affects the next value of the DBI bit. Specifically, in some instances, the value of the DBI bit is held to the immediately previous value of the DBI bit to limit the total number of transitions on a data bus.

Description

TECHNICAL FIELD[0001]This application relates to Data Bus Inversion (DBI), and more particularly, to systems and methods to minimize data transitions using DBI.BACKGROUND[0002]In single-ended parallel Input / Outputs (IOs) such as a Double Data Rate (DDR) transfer-mode bus, data bus inversion (DBI) is an increasingly popular coding scheme that reduces signaling power and simultaneous switching output (SSO) noise, thereby improving power and signal integrity. An example is an 8-bit data bus. In an 8-bit DBI-encoded data bus, the eight data bits are transmitted either as-is or inverted for each bit unit interval. At each bit unit interval, an extra coding overhead bit (also referred to as the DBI bit) accompanies the transmitted data bits to inform the receiver whether an intentional bus-wide inversion took place. For example, when the coding overhead bit is set to a logical one, it may indicate that the data bits of the bus are inverted. The receiver receives the data bits and the over...

AI Technical Summary

Benefits of technology

[0010]Various embodiments provide one or more advantages over conventional solutions. For instance, some embodiments improve upon the conventional DBI-AC scheme by additionally accounting for possible transitioning of the DBI bit. The result is the maximum number of transitions being no more than half of the data bus width. In an 8-bit data bus example, which is nine bits wide with the DBI bit, the maximum number of transitions with this improvement would be limited to four. This reflects a 20% maximum power reduction by virtue of limiting the maximum number of transitioning bits from five to four. Of course, the scope of embodiments is not limited to any particular number of bits in a bus. Such embodiments may further provide improved power integrity by reducing the current drawn from the supply or sent to ground

Problems solved by technology

Moreover, a large number of bit transitions may cause a phenomenon referred to as “ground bounce” or “supply bounce,” where the voltage supplied to a gate may temporarily dip and cause jitter.

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