Memory device and method of operation of such a memory device

Abstract

A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a memory device and to a method of operation of such a memory device, and in particular to a mechanism for operating such a memory device when the access circuitry used to access the array of memory cells is operated from a peripheral voltage domain with a supply voltage less than the supply voltage in a core voltage domain used by the array of memory cells.[0003]2. Description of the Prior Art[0004]In modern data processing systems, it is becoming more and more common for certain parts of the data processing system to operate in a different voltage domain to one or more other parts. For example, a trend within integrated circuits is the increasingly common use of embedded memory, such as SRAM memory. With the reduction in size of process geometries, the individual memory cells within the memory are becoming less stable. To reduce the power consumption of the integrated circuit, it is de...

AI Technical Summary

Benefits of technology

The patent describes a memory device that uses a dedicated level shifting circuit to level shift signals between different voltage domains. This circuit helps to ensure correct writing of data, even when there is a large difference in voltage between the different domains. However, this circuit comes with the drawback of increased power consumption and area usage. To address this, the patent suggests using a P / N skew to shift the drive strength of transistors in the circuit, which allows the circuit to level shift signals within a certain range. This reduces power consumption and the need for separate level shifting circuits. Additionally, the patent proposes controlling the precharge circuit and the write driver circuit using control signals that switch between a ground voltage level and the peripheral voltage level, which further reduces power consumption. The patent also mentions using a NAND circuit component with the P / N skew to increase the drive strength of NMOS transistors relative to PMOS transistors. Overall, the patent proposes various methods to reduce power consumption and improve the performance of memory devices.

Problems solved by technology

The level up shifting mechanism 40 is generally more problematic to implement than the level down shifting mechanism 50 (in fact in many instances no specific level down shifting circuitry may be required), since when performing level up shifting there is the potential for establishing various DC paths that can result in significant power consumption, and which may potentially create short circuit current paths.

In particular, it has been found that the write margin can be insufficient unless such level shifting has been performed.

Whilst this ensures correct operation, it has a significant impact on the overall power consumption of the memory device.

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