Memory device and method of operation of such a memory device

Abstract

A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a memory device and to a method of operation of such a memory device, and in particular to a mechanism for operating such a memory device when the access circuitry used to access the array of memory cells is operated from a peripheral voltage domain with a supply voltage less than the supply voltage in a core voltage domain used by the array of memory cells.[0003]2. Description of the Prior Art[0004]In modern data processing systems, it is becoming more and more common for certain parts of the data processing system to operate in a different voltage domain to one or more other parts. For example, a trend within integrated circuits is the increasingly common use of embedded memory, such as SRAM memory. With the reduction in size of process geometries, the individual memory cells within the memory are becoming less stable. To reduce the power consumption of the integrated circuit, it is de...

AI Technical Summary

Benefits of technology

[0012]By this approach, and in particular by asserting the word line signal and the mux control signal at the core voltage level, it has been found that sufficient write margin can be achieved to ensure write operations are performed correctly, even when the difference between the core voltage domain and the peripheral voltage domain is relatively large, for example 400 mV. However, since other control signals are retained at the peripheral voltage level, the overall power consumption of the memory device can be significantly reduced. For example, since the precharge circuitry precharges the bit lines only to the peripheral voltage level, rather than to the core voltage level, the power consumption associated with the discharging of certain bit lines during a write operation, and the subsequent precharging of those discharged bit lines back up to the peripheral voltage level prior to the next access operation, is significantly reduced.

[0016]Whilst in one embodiment the above-described dedicated level shifting circuits are used, such level shifting circuits occupy a relatively large area, and consume additional power to perform their level shifting operations. In an alternative embodiment, the requirement for such separate level shifting circuits can be avoided by instead applying a P / N skew to the transistors forming at least one of the components within the write multiplexing driver circuitry. In particular, in one embodiment, the write multiplexing driver circuitry comprises at least one circuit component formed of both NMOS transistors and PMOS transistors, and a drive strength of one of the NMOS transistors and the PMOS transistors is skewed so as to enable the write multiplexing driver circuitry to level shift at least one signal from the peripheral voltage level to the core voltage level in order to cause the asserted mux control signal to be at the core voltage level. Whilst the shifting range available from such a P / N skewing process is not as large as that available when using dedicated level shifting circuitry, it has been found that it can still provide a sufficient level shifting range to accommodate a 400 mV difference between the peripheral voltage domain and the core voltage domain, and accordingly can be used in order to reduce the area and power consumption associated with dedicated level shifting circuits.

[0017]In one particular embodiment, the write multiplexing driver circuitry includes a NAND circuit component and a P / N skew is incorporated within the NAND circuit component to increase the drive strength of the NMOS transistors relative to the PMOS transistors.

[0022]In one embodiment, operation of the precharge circuitry and the write driver circuitry is controlled by associated control signals switchable between a ground voltage level and said peripheral voltage level. Hence, the power consumption associated with these circuits is significantly reduced, when compared with driving those circuits using control signals that vary between the ground voltage level and the core voltage level.

[0023]Whilst each column may comprise a single bit line, in one embodiment each column is connected to a pair of bit lines. In that embodiment, the write driver circuitry may be configured to control the voltage on the pair of bit lines of each of the addressed memory cells during the write operation by maintaining one of the bit lines in said pair at the peripheral voltage level and discharging the voltage on the other of the bit lines in said pair. Since the bit lines are precharged to the peripheral voltage level, the power consumption involved in discharging one of the bit lines during the write operation is significantly reduced, when compared with an approach where the bit lines were precharged to the core voltage level. Further, the power consumption involved in subsequently precharging the discharged bit line is also reduced.

[0026]In one embodiment, operation of the precharge circuitry and the sense amplifier circuitry is controlled by associated control signals switchable between a ground voltage level and said peripheral voltage level, thereby reducing power consumption in those components when compared with a situation where the control signals are in the core voltage domain.

Problems solved by technology

The level up shifting mechanism 40 is generally more problematic to implement than the level down shifting mechanism 50 (in fact in many instances no specific level down shifting circuitry may be required), since when performing level up shifting there is the potential for establishing various DC paths that can result in significant power consumption, and which may potentially create short circuit current paths.

In particular, it has been found that the write margin can be insufficient unless such level shifting has been performed.

Whilst this ensures correct operation, it has a significant impact on the overall power consumption of the memory device.

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