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Methodology and Framework for Run-Time Coverage Measurement of Architectural Events of a Microprocessor

a microprocessor and run-time coverage technology, applied in the field of validation and verification testing, can solve the problems of large redundancy, complex coverage statistics, and inability to detect, and achieve the effect of reducing the amount of time and effective test cases

Inactive Publication Date: 2012-04-05
IBM CORP
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  • Application Information

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Benefits of technology

[0010]In one particular aspect, a utility performs run-time coverage measurement of architectural events in hardware under test, such as a processor, during a course of execution of a test case. The utility can be executed as a standalone tool or on an operating system environment. Methodologies perform by the utility can measure the coverage of maskable events using various data structures to save and reset maskable values. The maskable events are compared with an architecture state upon execution of an instruction, and the architecture state is restored. Run-time feedback can be provided of the architectural events to the test generator to generate effective test cases. The run-time feedback can enable coverage of all of the states in a reduced amount of time. A live view can be provided of the architectural event coverage data during the course of execution of the test case.

Problems solved by technology

The coverage statistics is complex and is not apparent from the test case.
Determining appropriate coverage in test case generators presents a lot of redundancy and creates enormous overhead in execution time.

Method used

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  • Methodology and Framework for Run-Time Coverage Measurement of Architectural Events of a Microprocessor
  • Methodology and Framework for Run-Time Coverage Measurement of Architectural Events of a Microprocessor
  • Methodology and Framework for Run-Time Coverage Measurement of Architectural Events of a Microprocessor

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Embodiment Construction

[0021]The illustrative embodiments provide a method, data processing system and computer program product to measure coverage statistics of architectural events of a processor integrated circuit (IC) at the instruction level. A test case is executed in a coverage mode by single-stepping, and the coverage statistics are accumulated on completion of execution of every instruction. The architectural event occurrences are reconstructed and recorded by analyzing the instruction (e.g., opcode, registers, data, etc.) and change in the architecture state after every instruction. Architecture state is tracked and modified where necessary to ensure that the events that could go unnoticed are recorded (e.g., setting of sticky bits). The disclosed innovation goes beyond single stepping and saving the state of the processor. Since the coverage measurement involves recording of various events, there are lot of instances in which the recording of events is not straightforward. Various detailed and ...

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Abstract

A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state changes are tracked and recorded. A mechanism to ensure capturing of maskable events is also provided. A feedback driven test-generation approach is enabled by the runtime coverage measurement. The runtime coverage measurement system presents a live view of the comprehensive architectural event coverage to the user / tester. The methodology can be implemented on an operating system environment and also as a standalone / bare-metal tool.

Description

BACKGROUND[0001]1. Technical Field[0002]The present disclosure relates generally validation and verification testing and more specifically to a method and system for coverage measure testing at an architectural level of integrated circuitry.[0003]2. Description of the Related Art[0004]Microprocessors are being built with complex architectures comprising a number of functional units. The state space of the processor architecture is very large, given the range of input values and architecture states in various execution units, such as Floating Point (FP) Units, vector units, and integer units and given the interaction between various units and the combination of events of various units. This huge state space necessitates extensive testing, while ensuring maximal coverage in minimal time. The coverage statistics is complex and is not apparent from the test case. Determining appropriate coverage in test case generators presents a lot of redundancy and creates enormous overhead in execut...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F9/30
CPCG06F11/2236
Inventor ALAPATI, SANGRAMSANKARANNAIR, JAYAKUMAR N.MALLIKARJUNAN, VARUNKUMAR, PRATHIBASADASIVAM, SATISH KUMAR
Owner IBM CORP
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