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Data access method employed in multi-channel flash memory system and data access apparatus thereof

a data access and multi-channel technology, applied in the direction of memory adressing/allocation/relocation, instruments, error detection/correction, etc., can solve the problems of reducing the data processing efficiency affecting the performance of the flash memory system, and affecting the data access delay time of the flash memory unit. , to achieve the effect of reducing the hardware manufacturing cost of the buffer unit and reducing the data access delay tim

Inactive Publication Date: 2010-10-14
JMICRON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0008]As mentioned above, the benefit of the present invention lies in utilizing the data access apparatus to perform data accessing (reading / writing) operations upon a plurality of flash memory units synchronously, thereby decreasing the data access delay time of the flash memory units effectively as well as decreasing the hardware manufacturing cost of the buffer unit.

Problems solved by technology

However, the data access delay time of the flash memory unit is much longer than the data transmission time between the host and the flash memory unit.
This longer data transmission time will inevitably decrease data processing efficiency of the flash memory system.

Method used

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  • Data access method employed in multi-channel flash memory system and data access apparatus thereof
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  • Data access method employed in multi-channel flash memory system and data access apparatus thereof

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Embodiment Construction

[0014]Please refer to FIG. 1 in conjunction with FIG. 2. FIG. 1 is a diagram illustrating a data access apparatus 100 according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating a data writing operation performed by the data access apparatus 100 shown in FIG. 1. As shown in FIG. 1, the data access apparatus 100 includes a buffer unit 105 and a control circuit 110. The data access apparatus 100 is used in a multi-channel flash memory system, and coupled to a plurality of flash memory units (e.g., an even number of flash memory units). The term “multi-channel” implies that the data access apparatus 100 is coupled to multiple flash memory units, and a host accesses the flash memory units synchronously through the data access apparatus 100. It should be noted that the number of flash memory units should not be considered as a limitation to the scope of the present invention. The buffer unit 105 includes a plurality of buffer areas. In this exemplary embodi...

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Abstract

A data access method used in a multi-channel flash memory system includes: respectively writing a plurality of data into a plurality of buffer areas of a buffer unit through direct memory accessing; and sequentially reading the plurality of data from the plurality of buffer areas, and respectively and synchronously storing the plurality of read data into the plurality of flash memory units, wherein each of the plurality of data is a data block protected by an error correction code (ECC).

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a data access mechanism, and more particularly, to a data access method employed in a multi-channel flash memory system and a data access apparatus thereof.[0003]2. Description of the Prior Art[0004]For a flash memory system, a host merely accesses one flash memory unit at a time, and accesses a next flash memory unit when the current flash memory unit is accessed completely. However, the data access delay time of the flash memory unit is much longer than the data transmission time between the host and the flash memory unit. Therefore, no matter whether the prior art design accesses only a single flash memory unit at a time or sequentially accesses a plurality of flash memory units, the conventional flash memory system needs to wait for a longer data transmission time to allow all of the flash memory units to finish reading or writing data. This longer data transmission time will inevita...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F12/00G06F12/02G06F13/28
CPCG06F11/1048G06F13/28
Inventor LIU, CHAO-YINLIU, CHIA-HUA
Owner JMICRON
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