Multilayer chip capacitor, motherboard apparatus having the same, and power distribution network

Abstract

There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged in a laminated direction; and first to fourth outer electrodes formed on side surfaces of the capacitor body, respectively, wherein the first capacitor unit includes first and second inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing a corresponding one of dielectric layers, the second capacitor unit includes third and fourth inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing another corresponding one of the dielectric layers, the first and second capacitor units are electrically insulated from each other, and the first capacitor unit operates in a first frequency range and the second capacitor unit operates in a second frequency range lower than the first frequency range.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the priorities of Korean Patent Application Nos. 2008-0030383 filed on Apr. 1, 2008 and 2008-0056543 filed on Jun. 16, 2008, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a multilayer chip capacitor, and more particularly, to a multilayer chip capacitor suitably used as a decoupling capacitor of a power distribution network of a digital switching circuit such as a micro processor unit (MPU) and capable of maintaining a power network distribution network impedance at a low level in a broad frequency range as a single capacitor, a motherboard apparatus having the same and a power distribution network.[0004]2. Description of the Related Art[0005]A power distribution network (PDN) of a micro processor unit (MPU) is designed with increasing difficulty due to higher ...

AI Technical Summary

Benefits of technology

[0012]An aspect of the present invention provides a multilayer chip capacitor capable of reducing a PDN impedance to a target impedance or less in a broad frequency range of hundreds of kHz to hundreds of MHz with a smaller number of capacitors.

[0014]An aspect of the present invention also provides a power distribution network which utilizes the multilayer chip capacitor to ensure easy design in a power distribution network and save costs and space required in designing and implementing the power distribution network.

Problems solved by technology

A power distribution network (PDN) of a micro processor unit (MPU) is designed with increasing difficulty due to higher speed and more integration of the MPU.

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