Logic device and method supporting scan test

Abstract

A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.

Description

BACKGROUND[0001]I. Field[0002]The present disclosure generally relates to systems and methods of scan testing.[0003]II. Description of Related Art[0004]Generally, an integrated circuit may include multiple digital logic circuits. One type of digital logic circuit is a flip-flop, which is a circuit that can be switched between two states. Flip-flop circuits are a common type of sequential circuit element used to build digital systems. Accordingly, flip-flop circuits may have an impact on both power and performance for such systems.[0005]Modern integrated circuits usually incorporate a variety of design-for-test (DFT) structures to enhance their inherent testability. Typically, the DFT structures are based on a scan design, where scan test data is provided to a test pin or where a plurality of externally accessible scan chains are embedded into the integrated circuit. When the scan chain is embedded, the scan chain may include one or more scan cells coupled in series, with each scan c...

AI Technical Summary

Benefits of technology

[0013]One particular advantage provided by embodiments of the particular logic device is that the test logic is removed from the data path of the logic device, reducing delays in the data path. In one particular embodiment, the delays may be reduced by up to 25 percent.

[0014]Another advantage is provided in that the logic device may consume less power than a conventional logic device with design for testability (DFT) features in the critical data path. Since the test logic is removed from the data path, the scan test logic may be gated in a power-off state during non-test operation. In one particular embodiment, the logic device may consume approximately 27 percent less power than a conventional logic device.

[0015]Still another advantage is that the test logic and the logic device are approximately the same physical size and may occupy approximately the same amount of area on a circuit substrate as conventional devices with DFT features.

Problems solved by technology

Unfortunately, to provide the data to the input, the test logic, such as a multiplexer, is typically placed within the data path of the logic circuit and may unnecessarily consume power during normal non-test operation.

Moreover, such test logic may introduce delays in the data path of the logic circuit, and the delays tend to reduce the performance of the logic circuit.

While pulsed latches may reduce the delay in the data path of the logic circuit, pulsed latches tend to consume more power and are typically less robust than flip-flops.

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