Semiconductor device

Abstract

The present invention provides an MOSFET having a semiconductor substrate, an insulating layer provided on the semiconductor substrate, and an SOI layer provided on the insulating layer. A source region and a drain region are provided in the SOI layer. A non-doped region is provided at a position interposed between the source region and the drain region in the SOI layer. A gate electrode is provided over the SOI layer through a gate insulating film interposed therebetween. The drain region is provided at a position offset from the gate electrode, the source region is provided at a position where it overlaps with the gate electrode, and the offset length of drain region ranges from over 10 nm to under 75 nm.

Description

BACKGROUND OF THE INVENTION [0001] The present invention relates to a semiconductor device, and particularly to a device structure of an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using an SOI (Silicon On Insulator) substrate. [0002] In an MOSFET (which might be also called “SOI-MOSFET” in the following description) formed in an SOI substrate, a so-called short channel effect in which as a gate length becomes shorter with the miniaturization of each 2 elemental device, a threshold voltage (Vth) falls, takes place. Since the short channel effect yields the deterioration of a variation in threshold voltage, it is important to suppress the short channel effect. It has been known that making an SOI layer thinner is effective in suppressing the short channel effect (refer to, for example, a non-patent document 1 (N. Kistler et al., Solid State Electronics, vol. 39, No. 4, pp. 445-454 (1996)). [0003] A structure of a generally-used conventional SOI-MOSFET will be explained...

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Benefits of technology

[0023] The present invention has been made in terms of the foregoing problems. An object of the present invention is to provide an MOSFET formed in an SOI substrate, which is capable of avoiding the occurrence of a conventional reduction in transistor drive power due to the introduction of an impurity, and suppressing a short channel effect.

[0026] According to an SOI-MOSFET showing a semiconductor device of the present invention, it has a drain offset structure in which a drain region is provided at a position offset from a gate electrode, and a source overlap structure in which a source region is provided at a position where it overlaps with the gate electrode. The offset length of drain region ranges from over 10 nm and under 75 nm. With such a configuration, a reduction in the drive power of a transistor due to the introduction of an impurity into a channel region can be avoided, and a short channel effect can be suppressed.

[0027] According to another semiconductor device of the present invention, it has a drain offset structure and a source offset structure in which a source region is provided at a position offset from a gate electrode. Further, the offset lengths of drain and source regions are set so as to range from over 2 nm to under 20 nm. It is therefore possible to avoid a reduction in the drive power of a transistor due to the introduction of an impurity into a channel region and suppress a short channel effect in a manner similar to the above.

Problems solved by technology

A problem, however, arises in that the breakdown voltage of the MOSFET is reduced when the thickness TSOI of the SOI layer 140 is made thin to suppress the short channel effect.

It is undesirable to reduce the breakdown voltage of the MOSFET in terms of its device characteristic.

Thus, when the body concentration Na exceeds 1×1018 cm−3, a reduction in the mobility (electron mobility in the case of an NMOS) of carriers presents a problem.

However, the semiconductor device (hereinafter might be also called “Non-doped SOI”) disclosed in the patent document 3, wherein no impurity is introduced into the channel region of the SOI layer, is not capable of controlling the threshold voltage Vth by the impurity concentration of the channel region 142.

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