Image sensor with digital frame store
a digital frame store and image sensor technology, applied in the field of monolithic integrated circuits, can solve the problems the link between the image sensor and the host processor must support the relatively high read-out data rate of the image sensor, etc., and achieve the effect of reducing the potential dynamic range of the pixel cell
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example 1
X=0, Y=0=>Address=0, Offset=0
RAM0_addr=0=>data out is Column 0, rows 0 to 3 RAM1_addr=0=>data out is Column 0, rows 4 to 7 final result is (LSB first) Column 0, rows 0 to 3, Column 0, rows 4 to 7 =Column 0, rows 0 to 7
example 2
X=N−1, Y=4=>Address=N−1, Offset=1
RAM0_addr=N−1+N (the extra+N due to Offset==1) =2N−1=>data out is Column N−1, rows 8 to 11 RAM1_addr=N−1=>data out is Column N−1, rows 4 to 7 final result is (LSB first) Column N−1, rows 4 to 7, Column N−1 rows 8 to 11 =Column N−1, rows 4 to 11
A layer of logical addressing sits over the physical addressing—the logical byte rows, which actually start at −2, are mapped to the physical rows starting at 0. This is done so that the 8-bytes accessed by the physical sub-sample address always contains the 5 bytes required for one column of the auto-levelling window centred around the pixel at the (x,y) coordinate.
This means that the first two byte rows in RAM0 are wasted, but this helps to simplify the design of the auto-level-threshold. The simplification comes from the fact that you can just use the Y coordinate of the row being auto-level-thresholded and you always get the two-rows above and the two-rows below.
The last two byte rows are also e...
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