Insulated-gate field-effect transistor, method of fabricating same, and semiconductor device employing same

Abstract

With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.

Description

[0001] 1. Field of the Invention[0002] The present invention relates to an insulated-gate field-effect transistor having high-mobility channel and a short gate length, and a method of fabricating the same. Further, the present invention is concerned with a semiconductor device employing the insulated-gate field-effect transistors. The transistor according to the present invention is useful when applied to a semiconductor device for use in an electronic circuit including a logic circuit, an analog circuit, and so on, particularly, in a field where high speed and low power consumption are required.[0003] 2. Description of the Related Art[0004] In the case of a silicon semiconductor device, particularly, a field effect transistor, larger scale integration of a circuit has so far been realized as well as obtained higher performance thereof by downsizing the device. However, upon a size of the gate of a transistor getting hyperfine to the extent of less than 50 nm, it has become extremel...

AI Technical Summary

Problems solved by technology

However, upon a size of the gate of a transistor getting hyperfine to the extent of less than 50 nm, it has become extremely difficult to achieve high performance through downsizing only.

With the conventional strained SOI, it has been impossible to sufficiently reduce the thickness of the layer upon the insulator layer because of the need for presence of the silicon germanium layer.

Accordingly, there has occurred a problem that a p-type transistor is more susceptible to occurrence of punch-through.

The strained SOI transistor tackled so far has had problems to be resolved.

Those are various barriers, particularly, to miniaturization of a device.

As can be seen from this example, with the conventional strained SOI, it has been impossible to sufficiently reduce the thickness of the channel layer because of the need for presence of the silicon germanium layer.

Further, there occurs another problem due to use of the silicon germanium layer to apply strain to silicon thereon.

Accordingly, an additional problem has been encountered that the p-type transistor of the structure as shown in this example is more susceptible to occurrence of punch-through.

Furthermore, substrates employed so far had a drawback that those have required a fabrication process using a special method of bonding together among other things, and consequently, fabrication cost thereof becomes higher in comparison with a conventional Si or SOI substrate.

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