PSK receiver, PSK demodulating circuit, communication apparatus, and PSK receiving method

Abstract

The invention provides a PSK receiver and a receiving method thereof, a PSK demodulating circuit and a communication apparatus, which can restrain the increase of the circuit scale and perform demodulation on phase modulated signals. As a solving means, an in-phase component (I) and an quadrature component (Q) contained in a reveived signal are converted to a 1-bit digital signal by 1-bit A / D converters (107, 108) respectively, when a phase point distance I-axes determined by the in-phase component (I) and the quadrature component (Q) is used as a predetermined region, a BPSK demodulator (110a) demoluates the received signal only according to the in-phase component (I), and when a phase point distance Q-axes determined by the in-phase component (I) and the quadrature component (Q) is used as a predetermined region, the BPSK demodulator (110a) demoluates the received signal only according to the quadrature component (Q).

Description

technical field [0001] The present invention relates to a kind of PSK (Phase Shift Keying, phase-shift keying) receiver and its receiving method, PSK demodulation circuit and communication device, especially relate to the in-phase (in phase) that is suitable for being converted into 1 bit digital signal Component I and Quadrature Component Q demodulation techniques. Background technique [0002] As a method of performing semi-synchronous detection (semi synchronous detection) in PSK demodulation, there is a method of performing carrier synchronization and demodulation based on the received in-phase component I and quadrature component Q (Patent Document 1). The method of applying the following formula (1) to the component I and the quadrature component Q to obtain the phase θ and perform carrier synchronization for demodulation (Patent Document 2). [0003] θ=tan-1(I / Q)...(1) [0004] Patent Document 1 Japanese Patent Application Laid-Open No. 2001-24726 [0005] Patent D...

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Problems solved by technology

[0006] However, in the method disclosed in Patent Document 1, carrier synchronization is realized based on the in-phase component I and the quadrature component Q, so complex multiplication is required for phase correction of the received signal, and complex multiplication requires four multipliers, so there is The problem of increased circuit size

In addition, in the method disclosed in Patent Document 2, the phase θ is obtained from the received in-phase component I and quadrature component Q, so it is necessary to perform the calculation of the formula (1), and a large-capacity ROM is required, so there is a problem that the circuit scale becomes larger. The problem

[0007] In addition, in the above-mentioned two methods, a multi-bit AD converter is required for phase correction, and there is a problem of further enlarging the circuit scale.

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