System for testing clock signal dither and method thereof

Abstract

The present invention relates to an on-chip system for testing clock signal flutter and its method, in particular, it relates to test of phase-locked loop flutter. The high time analyticity, low amplitude and differential signal are not influenced by element changeability. It includes subthreshold current control one-sided delay line with N time-delay units, reference delay line and test clock delay line. Besides, it also includes a arbiter and a calibrator. Said invention also provides the concrete steps of its test method.

Description

technical field [0001] The invention relates to an integrated circuit on-chip test system and test method, in particular to an on-chip system and method for testing clock signal jitter, especially to a phase-locked loop jitter test system and method. Background technique [0002] The current main development trend of integrated circuits is high speed, low power consumption, and small area. With the continuous improvement of the speed of digital circuits, the design of high-frequency clocks has become the main contradiction. In large-scale digital integrated circuits, even more than half of the The area is used for the clock tree circuit. In order to realize high-frequency clock frequency and other designs related to high-frequency applications, a phase-locked loop circuit (PLL) is required to realize the synchronization of the clock circuit in most occasions. The meaning of phase locking is the automatic control of phase synchronization. The automatic control closed-loop sy...

AI Technical Summary

Problems solved by technology

In order to solve the problem of the linearity limitation of the variable delay line, a delay line architecture that is not affected by component variability can be used, but the disadvantage is that it requires a long test time

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