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Trap charge capturing quick flashing storage array structure and operating method thereof

A technology of memory array and trap charge, which is applied in the field of trap charge-trapping flash memory array structure, can solve the problems of inability to program selectively at the source end and cannot realize double-bit storage, achieve high integration, improve consistency, and improve The effect of capacity

Inactive Publication Date: 2006-10-18
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the use of a common source line structure, selective programming of the source cannot be performed, and double-bit storage of each unit cannot be realized.

Method used

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  • Trap charge capturing quick flashing storage array structure and operating method thereof
  • Trap charge capturing quick flashing storage array structure and operating method thereof
  • Trap charge capturing quick flashing storage array structure and operating method thereof

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Embodiment Construction

[0053] The invention proposes a charge-trapping flash memory array structure and an operation method thereof. The specific implementation manner of the present invention will be described below in conjunction with the accompanying drawings.

[0054] Figure 5 What is shown is a schematic diagram of the array structure suitable for the SONOS flash memory proposed by the present invention. The m SONOS flash memory cell strings are connected together to form the SONOS cell string STi. The number m of units in each unit string is not limited to 16 as shown in the figure. A series of SONOS cell strings STi are respectively arranged in the row direction and the column direction to form a memory array. Each cell string also includes a bit line selection transistor 501D and a source line selection transistor 501S. In the row direction, the gate of each SONOS unit is commonly connected to a word line WLx (WL0 to WL15), and at the same time, the gate of each bit line selection trans...

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PUM

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Abstract

The present invention relates to a trap charge captured type flash memory array structure and its operation method. Said invention adopts serial arrangement to arrange the serial memory array structure forming two-dimensional several repeated permutations on the substrate. Said structure includes a first selective transistor, several storage units and a second selective transistor, the transistors and storage units are serial-connected, the gate of storage unit is connected with word line, the gate of selective transistor is connected with selection line, and first end of said serial structure is connected with bit line, and its second end is connected with next adjacent bit line. Its operation method includes programming operation, erasion operation and fetch operation.

Description

technical field [0001] The invention belongs to the technology of non-volatile memory, and in particular relates to an array structure in a SONOS (silicon-oxide layer-nitride layer-oxide layer-silicon) type flash memory and a kind of trapped charge trapping for programming, erasing and reading operations Flash memory array structure and method of operation thereof. Background technique [0002] Flash memory has the characteristic that the stored data will not be lost after power failure, and is especially suitable for fields such as mobile communication and computer storage components. Some flash memories also have high-density storage capabilities, and are suitable for applications such as large-capacity mobile storage media. [0003] A conventional flash memory has a floating gate structure, which includes a tunnel oxide layer, a floating gate, a dielectric layer between the floating gate and the control gate, and a control gate. The flash memory technology of this float...

Claims

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Application Information

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IPC IPC(8): G11C16/02H10B43/30
Inventor 潘立阳孙磊朱钧
Owner TSINGHUA UNIV
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