Method and apparatus for realizing multipath signal re-timing

Abstract

The invention discloses a method for achieving multi-path signal re-timing, especially to the re-timing of multi-path E1, T1 or other low speed signal. It uses a high speed clock source to generate a high frequency clock signal as system clock; the system clock generates a plurality of time slots; each time slot comprises a plurality of system clock periods; it separately stores the sampled low speed signal data in RAM and reads the data of all the paths of a time slot, which achieves each path synchronic processing.

Description

technical field [0001] The invention relates to the communication field, in particular to a realization method for processing multiple asynchronous signals into multiple synchronous signals. Background technique [0002] SDH system (Synchronous Digital Communication Transmission System) is widely used in important transmission systems such as modern high-speed telecommunication networks and high-speed Internet, and is of great significance to the development of optical fiber, microwave and satellite communication technologies. In the SDH system, data adaptation needs to be adjusted by mapping or pointers. However, during this adjustment process, data jitter and drift will be introduced. In order to avoid and reduce the impact on synchronization timing when this happens, it is necessary to perform Signal timing processing. [0003] see figure 1 , which is a schematic structural diagram of an SDH system. In the local transmission network layer, SDH rings mostly use multiple...

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Problems solved by technology

[0009] The purpose of the present invention is to provide a method and device for retiming multi-channel signals, so as to solve the technical problems of high cost and serious waste of resources in the prior art

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