Four path parallel clock data restoring circuit

Abstract

A four-channel parallel clock data resuming circuit includes a clock resuming phase-lock loop, three data delay phase-lock loops and a data resuming circuit, among which, the second channel input data is connected with the input of the clock resume phase-lock loop, which outputs the global clock signal, the global clock is aligned with the second channel input data and connected with the clock input ends of three data delay phase-lock loops, the input data of the other three channel input data are connected with the data input ends of the three data delay phase-lock loops, the three resume phase lock loops align the three channels of data signals with the global clock to realize the alignment of the four channels connected with the input of the resuming circuit, the global is connected with its clock input finally to output four channels of bit synchronous data signals and a global clock signal.

Description

technical field [0001] The invention is used in a receiver of a high-speed parallel optical communication system to realize a four-channel parallel clock data recovery function, and belongs to the technical field of optical communication equipment. Background technique [0002] In modern 4-channel parallel optical communication systems, 4 parallel optical fibers are used as channels for data transmission. The sending end sends out 4 parallel data signals. The channel is composed of 4 mutually independent optical fibers arranged side by side. The 4 channels of parallel data are respectively transmitted to the receiving end through a corresponding optical fiber. Since the transmission characteristics of the 4 channels of parallel fiber optic channels cannot be completely consistent in practical applications, there is a time delay difference between the 4 channels of data signals when they reach the receiving end. Therefore, the 4 channels of data received by the receiving en...

AI Technical Summary

Problems solved by technology

The problem with this scheme is that each channel performs clock recovery independently of each other, and the local clock recovered by each channel is not synchronized

This will cause two problems: First, the data recovered by each channel is not synchronized. In order to output clock and data signals with correct phase relationship to the subsequent circuit, each channel needs to use source synchronous output, that is, output a high-speed data signal and a high-speed clock signal

In this way, 4 channels output 4 clocks and 4 channels of data in total, which increases the complexity of system wiring

Secondly, since the clock data recovery is performed independently on each channel, the delay difference between the four data signals caused by the difference in the transmission characteristics of each channel of the parallel fiber channel has not been processed. Therefore, this delay difference is transmitted to the subsequent circuit, which will Reduce the phase margin of subsequent digital sampling circuits

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