Self-timed reliability and yield vehicle with gated data and clock

A technology for gating clock and data, applied in the direction of semiconductor device, electric solid state device, single semiconductor device testing, etc., can solve the problems of slow test, unreliable test, increase cycle, etc., and achieve the effect of improving production process

Active Publication Date: 2010-06-23
AVAGO TECH WIRELESS IP SINGAPORE PTE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] Defect tester systems available on the market, such as the PDF solution and the KLA microcircuit structure using SEM or optical inspection, are slow to test and cannot be used for reliability testing, and increase the cycle time if used
[0013] Failure analysis, especially for 90nm and beyond, is becoming extremely difficult

Method used

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  • Self-timed reliability and yield vehicle with gated data and clock
  • Self-timed reliability and yield vehicle with gated data and clock
  • Self-timed reliability and yield vehicle with gated data and clock

Examples

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Embodiment Construction

[0045] figure 1An embodiment 100 of a self-timed resistive fault test vehicle is shown in which integrated circuits are tested for resistive fault reliability and production and fault location is determined. Column clock circuit 104 receives signals from an NxN multiplexer (MUX) and a first column 112 of interconnect module 101 array. This first column serves as a self-timing circuit that takes a clock edge (usually from a lower speed clock signal) and generates pulses of a certain duration, which are then used to time the N× The speed of the N multiplexers and other columns within the interconnect subarray 101. The output of the other columns is loaded into the column scan trigger logic 108 using this timed pulse and the difference is registered. A signal registered at column scan trigger logic 108 other than the first column of self-timing circuit 112 indicates the presence of an irregularity, defect, or some kind of error in a particular column.

[0046] Similarly, row c...

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PUM

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Abstract

A test vehicle, system and method for evaluating an interconnect module manufacturing process while dynamically testing performance with high-speed operational frequencies are disclosed. The test vehicle incorporates a self-timed or gated speed circuit that can detect subtle resistive faults and also show the exact location in the array where the speed fault occurred based on test program data logs from scan flip flops. One embodiment incorporates a gated clock in the gated speed circuit producing gated data that delivers greater statistical properties with respect to Integrated Circuit Direct Drain Quiescent Current (IDDQ) testing.

Description

[0001] Cross References to Related Applications [0002] This application is a continuation-in-part of U.S. Patent Application Serial No. 10 / 418,560 (filed April 16, 2003 by Richard Schnltz), entitled "Self-Timed Reliability and Product Carriers," and is hereby in its entirety for all its disclosures and teachings incorporated herein by reference. field of invention [0003] This invention relates to the manufacture of integrated circuits, and more particularly to test samples for qualifying new production processes. Background technique [0004] In the development of a new production process for integrated circuits (interconnected modules), certain design rules are established to define the capabilities of the process. While production capacity is being developed, designers begin the design of new integrated circuits. Consistency of new process development and production design is of paramount importance to the ability to generate integrated circuit production processes u...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66H01L23/544H01L27/02G01R31/26G01R31/28
Inventor R·舒尔茨D·奥曼J·富瑞
Owner AVAGO TECH WIRELESS IP SINGAPORE PTE
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