IP nuclear simulation confirmation platform based on PCI bus and proving method thereof

A PCI bus, simulation verification technology, applied to the PCI bus-based IP core simulation verification platform and its verification field, can solve problems such as difficulty in collecting test results, unfavorable real-time monitoring of the test process, difficulty in generating and controlling test signals, etc., to achieve design Reasonable, easy to use, and simple hardware structure

Inactive Publication Date: 2005-04-27
SOUTH CHINA UNIV OF TECH
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Problems solved by technology

This method can effectively test the logical function of IP and its correctness in the actual circuit, but it also has certain disadvantages: when performing hardware verification in FPGA, it is difficult to generate and control a large number of test signals for testing IP, not only difficult to collect test results, and it is not conducive to real-time monitoring of the test process

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  • IP nuclear simulation confirmation platform based on PCI bus and proving method thereof
  • IP nuclear simulation confirmation platform based on PCI bus and proving method thereof
  • IP nuclear simulation confirmation platform based on PCI bus and proving method thereof

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Embodiment Construction

[0027] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

[0028] Such as figure 1 As shown, the verification method of the general soft IP core refers to the software simulation in the software environment to verify the correctness of the IP core function, and then write it into the FPGA device for hardware testing. If the test is correct, the IP core verification is completed. If there is a problem in the test, return to re-modify the IP core. The disadvantage of this method is: when performing hardware verification in FPGA, it is difficult to generate and control a large number of test signals for testing IP, not only difficult to collect test results, but also not conducive to real-time monitoring of the test process.

[0029] Such as figure 2 As shown, the PCI bus control module is a bridge module of the PCI bus, which is connected to the PCI slot of the computer and connected to the IP module...

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Abstract

The IP kernel simulating verification platform based on PCI bus includes crystal vibrator, DC voltage regulator, FPGA, programming interface, SDRAM and PCI interface. The verification process includes describing IP kernel system in Verilog HDL language, interconnecting the top layer simulating modules with PCI bus, interconnecting hardware modules with internal bus the same as that in SoC inside the chip, embedding verified IP kernel into the verification platform, and controlling the platform to test IP kernel in PC. The present invention has verification platform with simple structure and convenient use, and verification process capable of simulating effectively SoC environment of IP, utilizing FPGA and PC in the hardware verification of IP, real-time creating test data for IP kernel to test and real-time accessing the register and memory inside IP kernel to obtain the verification finishing data.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to an IP core simulation verification platform based on a PCI (Peripheral Component Interconnection) bus and a verification method thereof. Background technique [0002] The verification method of the general soft IP core refers to performing software simulation in a software environment to verify the correctness of the IP (Intellectual Property) core function, and then writing it into the FPGA (Field Progamable Gate Array) device to verify the hardware circuit. After the IP core verification is completed, if there is a problem in the test, return to re-modify the IP core. This method can effectively verify the logical function of IP and its correctness in the actual circuit, but it also has certain disadvantages: when performing hardware verification in FPGA, it is difficult to generate and control a large number of test signals for testing IP...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/00G06F17/50
Inventor 郑学仁范健民陈玲晶陈国辉邓婉玲
Owner SOUTH CHINA UNIV OF TECH
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