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Latching effect detecting method for CMOS circuit

A test method and technology of latch-up effect, applied in the field of testing, can solve the problems of complex trigger source pulse waveform and inconvenient actual use, and achieve the effect of reducing design cost and use risk, and simple pulse waveform

Active Publication Date: 2005-03-02
CHINA ELECTRONICS PROD RELIABILITY & ENVIRONMENTAL TESTING RES INST THE FIFTH ELECTRONICS RES INST OF MIITCEPREI LAB
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  • Abstract
  • Description
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Problems solved by technology

Moreover, the test process adopted by this method and the trigger source pulse waveform applied in the test process are relatively complicated, which is not very convenient in actual use.

Method used

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  • Latching effect detecting method for CMOS circuit
  • Latching effect detecting method for CMOS circuit
  • Latching effect detecting method for CMOS circuit

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Embodiment Construction

[0032] see Figure 8 As shown, the latch-up test method of the CMOS circuit of the present invention can be used for testing the trigger voltage / current of the CMOS integrated circuit, the accurate value of the maintenance voltage / current and the secondary breakdown voltage / current anti-latch-up ability parameter, firstly during the test Connect all the input terminals of the device under test to the ground, and the output terminals are suspended, and then proceed as follows:

[0033] Step 1: First, perform a DC voltage scanning test on the terminal to be tested until the terminal to be tested conducts to the ground, and obtain the trigger voltage Von of the terminal to be tested. During specific implementation, the scanning range of the DC voltage can start from 0V, the step size is 0.5V, and the current limit is 50mA. It can be seen from the IV characteristics of the power supply terminal that the current is very small when the voltage is less than a certain value, and the ...

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Abstract

The invention relates to a measuring method for latching effect of CMOS circuit, which can be applied to measure the igniting voltage / current of CMOS integrated circuit, maintaining the accurate value of the voltage and current, and the latching resisting ability parameter of secondary breakdown voltage and current. When in test, the input ends of the device being to be measured are grounded, the output ends suspends, then carries on following steps: at first, carries on direct current voltage scanning test to the terminal needed to be measured until the terminal is conducted to the ground, acquires the igniting voltage Von; then, carries on pulse current Ipulse test to the measured terminal until the latching appears, acquires the voltage and current; finally, carries on pulse voltage Vpulse test to measured terminal until appearing the secondary breakdown, and acquires the secondary breakdown voltage and current.

Description

【Technical field】 [0001] The invention relates to a test method, in particular to a latch-up effect test method for CMOS circuits. 【Background technique】 [0002] At present, most of the CMOS integrated circuits need to be tested for anti-latch-up ability before leaving the factory, so as to judge the impact of the latch-up on the integrated circuit. The standard for testing the anti-latch-up ability of CMOS integrated circuits is mainly JEDEC78. At present, there are instruments and equipment designed and manufactured according to this standard in foreign countries to test the anti-latch-up ability of CMOS integrated circuits. Please refer to figure 1 shown. Among them, the ATE test refers to the test of automatic test equipment (Auto Test Equipment), which can test the functions and parameters of the device under test. The ATE test is performed once before and after the real latch-up resistance test to ensure the accuracy of the latch-up resistance test. Performing the ...

Claims

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Application Information

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IPC IPC(8): G01R31/28
Inventor 罗宏伟
Owner CHINA ELECTRONICS PROD RELIABILITY & ENVIRONMENTAL TESTING RES INST THE FIFTH ELECTRONICS RES INST OF MIITCEPREI LAB
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