Integrated circuit layout plan and buffer plan integrated layout method

Abstract

The invention is a distribution method integrating the integrated circuit distribution plan and the buffer plan, the invention belongs to computer aided design for integrated circuit field. The character lies in: it introduces the feasible area calculation when the buffer is inserted in, and simplifies the complexity of the buffer distribution through distribution of the blank area in the plan result, the design is carried on pointing to the solution procedure to the simulated quenching by the buffer distribution, the distribution of the buffer is integrated in the solution of the distribution plan. The buffer distribution is leaded in the optimization process of the wiring plan, realizes the optimization to the delay performance.

Description

technical field [0001] The integrated layout method for integrated circuit layout planning and buffer planning belongs to the field of integrated circuit computer-aided design, in particular to the field of BBL (Building Block Layout). Background technique [0002] In the layout of integrated circuits, hierarchical layout design, module reuse technology, a large number of applications of intellectual property modules, the design of system-on-chip especially digital-analog hybrid system-on-chip, and analog circuit device-level layout problems, these problems can all be It boils down to the problem of floorplanning and layout of integrated circuit macro modules, namely Building Block Layout: the layout problem of BBL mode, which has become a current research hotspot. In particular, as the proportion of interconnect lines in the layout becomes larger and larger, the traditional layout planning method ignores the consideration of the layout, resulting in the inability to meet th...

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Judging from the obtained results, there is still a very large gap with the actual application.

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